test(asm): seed the riscv64 and loong64 assemble fuzz targets
Assisted-by: GLM 5.3
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+84
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Seed corpus for FuzzAssembleLOONG64: the ll/sc and pointer load/store
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// offset ladder, the three spans the encoder classifies by (a signed 16-bit
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// offset alone, a 32-bit one split through addu16i.d into R30, a wider one
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// materialised in full), the acquire/release pair, sc.q and the atomics with
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// their dbar forms.
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#include "textflag.h"
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TEXT ·llscNear(SB), NOSPLIT, $0
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LL (R12), R13
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LL 0(R12), R13
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LL 4(R12), R13
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LLW 8(R12), R13
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LLW -4(R12), R13
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LLV 8(R14), R15
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LLV -8(R14), R15
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SC R16, (R17)
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SC R16, 0(R17)
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SCW R16, 4(R17)
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SCV R18,-8(R19)
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RET
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TEXT ·llscSpans(SB), NOSPLIT, $0
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LL 1020(R12), R13
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LL 1024(R12), R13
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LL -1024(R12), R13
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LLW 32760(R12), R13
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LLW 32764(R12), R13
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LLW 32768(R12), R13
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LLW -32768(R12), R13
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LLV 65532(R14), R15
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LLV 65536(R14), R15
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LLV 131068(R14), R15
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LLW 1048572(R12), R13
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LLV 2147483644(R14), R15
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LLV -2147483648(R14), R15
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SC R16, 1020(R17)
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SCW R16, 32764(R17)
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SCV R18, 65532(R19)
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SCV R18, 65536(R19)
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RET
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TEXT ·ptrForms(SB), NOSPLIT, $0
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MOVWP R16, (R17)
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MOVWP R16, 8(R17)
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MOVVP R18, (R19)
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MOVVP R18,-8(R19)
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RET
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TEXT ·acqRel(SB), NOSPLIT, $0
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LLACQW (R5), R4
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LLACQV (R5), R4
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SCRELW R4, (R6)
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SCRELV R4, (R6)
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SCQ R4, R5, (R6)
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RET
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TEXT ·atomics(SB), NOSPLIT, $0
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AMSWAPB R14, (R13), R12
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AMSWAPH R14, (R13), R12
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AMSWAPW R14, (R13), R12
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AMSWAPV R14, (R13), R12
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AMCASB R14, (R13), R12
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AMCASDBV R14, (R13), R12
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AMADDW R14, (R13), R12
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AMADDV R14, (R13), R12
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AMANDW R6, (R5), R4
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AMORW R0, (R5), R4
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AMXORV R14, (R13), R12
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AMMAXW R14, (R13), R12
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AMMINV R14, (R13), R12
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AMMAXWU R14, (R13), R12
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AMMINVU R14, (R13), R12
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AMADDDBW R14, (R13), R12
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AMADDDBV R14, (R13), R12
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AMANDDBW R6, (R5), R4
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AMORDBV R14, (R13), R12
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AMXORDBW R14, (R13), R12
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AMMAXDBWU R14, (R13), R12
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AMMINDBVU R14, (R13), R12
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RET
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+212
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Seed corpus for FuzzAssembleLOONG64: the LSX (V) and LASX (X) register
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// banks, the family GOROOT's loong64 assembler corpus exercises
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// (cmd/asm/internal/asm/testdata/loong64enc*.s). Every immediate window sits
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// on an encoder gate: the si5 compares, the biased shifts, the ui8 logic
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// immediates and the element moves.
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#include "textflag.h"
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TEXT ·vecArith(SB), NOSPLIT, $0
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VADDV V1, V2, V3
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VADDW V1, V2, V3
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VADDD V1, V2, V3
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VADDQ V1, V2, V3
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VSUBV V1, V2, V3
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VSSUBV V1, V2, V3
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VSADDVU V1, V2, V3
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VMULV V1, V2, V3
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VMUHVU V1, V2, V3
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VDIVB V1, V2, V3
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VMODH V1, V2, V3
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VANDV V1, V2, V3
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VORV V1, V2, V3
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VXORV V1, V2, V3
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VNORV V1, V2, V3
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VANDNV V1, V2, V3
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VSEQB V1, V2, V3
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VSLTW V1, V2, V3
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VSLTBU V1, V2, V3
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VSLLB V1, V2, V3
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VSRAH V1, V2, V3
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VROTRV V1, V2, V3
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VILVLW V1, V2, V3
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VILVHV V1, V2, V3
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VBITCLRW V1, V2, V3
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VBITSETB V1, V2, V3
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VBITREVW V1, V2, V3
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VADDWEVHB V1, V2, V3
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VSUBWODVW V1, V2, V3
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VMULWEVQV V1, V2, V3
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VMADDWODQVU V1, V2, V3
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VSHUFV V1, V2, V3
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RET
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TEXT ·vecArithX(SB), NOSPLIT, $0
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XVADDV X1, X2, X3
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XVADDW X1, X2, X3
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XVADDD X1, X2, X3
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XVADDQ X1, X2, X3
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XVSUBV X1, X2, X3
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XVSSUBVU X1, X2, X3
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XVMULV X1, X2, X3
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XVMUHVU X1, X2, X3
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XVDIVB X1, X2, X3
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XVANDV X1, X2, X3
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XVNORV X1, X2, X3
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XVSEQB X1, X2, X3
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XVSLTW X1, X2, X3
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XVSLLB X1, X2, X3
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XVSRAB X1, X2, X3
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XVROTRW X1, X2, X3
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XVILVLB X1, X2, X3
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XVBITCLRV X1, X2, X3
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XVADDWEVHB X1, X2, X3
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XVMULWODWHU X1, X2, X3
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XVMADDWEVQVUV X1, X2, X3
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XVSHUFV X1, X2, X3
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RET
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TEXT ·vecImm(SB), NOSPLIT, $0
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VANDB $0, V2, V3
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VANDB $255, V2, V3
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VORB $128, V2, V3
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VXORB $255, V2, V3
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VNORB $1, V2, V3
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VSEQB $-16, V2, V3
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VSEQB $15, V2, V3
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VSEQH $0, V2, V3
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VSEQW $-1, V2, V3
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VSEQV $15, V2, V3
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VSEQV $-15, V2, V3
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VSLTB $-16, V2, V3
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VSLTBU $0, V2, V3
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VSLTBU $31, V2, V3
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VADDBU $0, V2, V3
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VADDVU $31, V2, V3
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VSUBBU $31, V2, V3
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VSLLB $0, V2, V3
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VSLLB $7, V2, V3
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VSLLH $15, V2, V3
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VSLLW $31, V2, V3
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VSLLV $63, V2, V3
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VSRLB $7, V2, V3
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VSRAB $7, V2, V3
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VSRAH $15, V2, V3
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VSRAW $31, V2, V3
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VSRAV $63, V2, V3
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VROTRB $7, V2, V3
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VROTRH $15, V2, V3
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VROTRW $31, V2, V3
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VROTRV $63, V2, V3
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VBITCLRB $7, V2, V3
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VBITSETH $15, V2, V3
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VBITREVW $31, V2, V3
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VBITREVV $63, V2, V3
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XVANDB $0, X2, X3
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XVANDB $255, X2, X3
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XVSEQB $-16, X2, X3
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XVSEQB $15, X2, X3
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XVSEQV $15, X2, X3
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XVADDVU $31, X2, X3
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XVSLLB $0, X2, X3
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XVSLLB $7, X2, X3
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XVSLLV $63, X2, X3
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XVSRAB $7, X2, X3
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XVROTRV $63, X2, X3
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XVBITCLRB $7, X2, X3
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XVBITSETV $63, X2, X3
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RET
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TEXT ·vecUnary(SB), NOSPLIT, $0
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VPCNTB V1, V2
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VPCNTH V1, V2
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VPCNTW V1, V2
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VPCNTV V1, V2
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VNEGB V1, V2
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VNEGW V1, V2
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VNEGV V1, V2
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VFCLASSF V1, V2
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VFCLASSD V1, V2
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VFSQRTF V1, V2
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VFSQRTD V1, V2
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VFRECIPD V1, V2
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VFRSQRTF V1, V2
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VFRINTF V1, V2
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VFRINTRMD V1, V2
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VFRINTRNEF V1, V2
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VFRINTRZD V1, V2
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VFRINTRPF V1, V2
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XVPCNTB X1, X2
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XVPCNTV X1, X2
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XVNEGH X1, X2
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XVFSQRTD X1, X2
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XVFRECIPF X1, X2
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XVFRINTRZD X1, X2
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RET
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TEXT ·vecCond(SB), NOSPLIT, $0
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VSETNEV V1, FCC0
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VSETEQV V1, FCC1
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VSETANYEQB V1, FCC2
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VSETANYEQH V2, FCC3
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VSETANYEQW V1, FCC4
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VSETANYEQV V2, FCC5
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VSETALLNEB V1, FCC6
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VSETALLNEH V2, FCC7
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VSETALLNEW V1, FCC0
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VSETALLNEV V0, FCC1
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XVSETNEV X1, FCC0
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XVSETEQV X2, FCC1
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XVSETANYEQV X1, FCC2
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XVSETALLNEB X2, FCC3
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RET
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TEXT ·vecShuffle4(SB), NOSPLIT, $0
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VSHUFB V0, V1, V2, V3
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XVSHUFB X0, X1, X2, X3
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RET
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// The VMOVQ/XVMOVQ move family: the load, the indexed load, the store, the
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// replicated load, the whole-register move, the GPR broadcast, the element
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// extract, the element insert and the element broadcast.
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TEXT ·vecMove(SB), NOSPLIT, $0
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VMOVQ 8(R4), V2
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VMOVQ (R4)(R5), V2
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VMOVQ V2, 8(R4)
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VMOVQ V2, (R4)(R5)
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VMOVQ 2(R4), V1.H8
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VMOVQ -6(R4), V1.H8
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VMOVQ -12(R4), V2.W4
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VMOVQ V1, V2
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VMOVQ R4, V1.B16
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VMOVQ R4, V1.H8
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VMOVQ R4, V1.W4
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VMOVQ R4, V1.V2
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VMOVQ V1.B[3], R5
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VMOVQ V1.H[7], R5
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VMOVQ V1.W[3], R5
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VMOVQ V1.V[1], R5
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VMOVQ R5, V1.B[3]
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VMOVQ R5, V1.H[7]
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VMOVQ R5, V1.W[3]
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VMOVQ R5, V1.V[1]
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VMOVQ V1.B[3], V9.B16
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VMOVQ V2.H[2], V8.H8
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VMOVQ V3.W[1], V7.W4
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VMOVQ V4.V[0], V6.V2
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XVMOVQ X1, X2
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XVMOVQ X0, X31.B32
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XVMOVQ X1, X30.H16
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XVMOVQ X2, X29.W8
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XVMOVQ X3, X28.V4
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XVMOVQ X3, X27.Q2
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XVMOVQ X0, X31.W[7]
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XVMOVQ X1, X29.W[0]
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XVMOVQ X3, X28.V[3]
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XVMOVQ X4, X27.V[0]
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XVMOVQ X31.W[7], X0
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XVMOVQ X28.V[3], X8
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RET
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+121
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Seed corpus for FuzzAssembleLOONG64: the branches over their offset range,
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// the jumps, the bit-field pair at the msb/lsb boundaries, the ALSL shift
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// window, RDTIME, the system instructions, the constant materialisation
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// chain and the register-class moves.
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#include "textflag.h"
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TEXT ·branches(SB), NOSPLIT, $0
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BEQ R4, R5, b1
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BNE R4, R5, b2
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BLT R4, R5, b1
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BGE R4, R5, b2
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BLTU R4, R5, b1
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BGEU R4, R5, b2
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BEQZ R6, b1
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BNEZ R7, b2
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BLTZ R8, b1
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BGEZ R9, b2
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BLEZ R10, b1
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BGTZ R11, b2
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BFPT b1
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BFPF b2
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b1:
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MOVV R1, R2
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b2:
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MOVV R2, R1
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BEQ R4, R5, b1
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RET
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TEXT ·jumps(SB), NOSPLIT, $0
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JMP j1
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JAL (R30)
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JIRL R0, R4, 8
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JIRL R1, R5, 0
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CALL runtime·morestack_noctxt(SB)
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j1:
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JMP -3(PC)
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RET
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TEXT ·bitfield(SB), NOSPLIT, $0
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BSTRINSW $3, R4, $0, R5
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BSTRINSV $7, R4, $0, R5
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BSTRINSV $31, R6, $0, R7
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BSTRINSV $63, R6, $32, R7
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BSTRPICKW $3, R4, $0, R5
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BSTRPICKV $6, R7, $0, R8
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BSTRPICKV $63, R6, $32, R7
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ALSLW $1, R4, R5, R6
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ALSLW $4, R7, R8, R9
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ALSLWU $3, R4, R5, R6
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ALSLV $2, R8, R9, R10
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ALSLV $3, R8, R9, R10
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RET
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TEXT ·system(SB), NOSPLIT, $0
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SYSCALL
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DBAR
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DBAR $0
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BREAK $0
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BREAK $32767
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PRELD 0(R4), $0
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PRELD 2047(R4), $31
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RDTIMELW R7, R8
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RDTIMEHW R7, R8
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RDTIMED R20, R21
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RET
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TEXT ·consts(SB), NOSPLIT, $0
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LU12IW R4, $0x12345
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LU12IW R5, $-524288
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LU12IW R6, $1048575
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LU32ID R7, $-524288
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LU52ID $-4096, R8, R9
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LU52ID $4095, R8, R9
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PCALAU12I R10, $0x12345
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PCADDU12I R11, $-524288
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ADDV16 $65536, R11, R12
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ADDV16 $-65536, R11, R12
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MOVV $0x123456789ABCDEF0, R13
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MOVV $-1, R14
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RET
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TEXT ·regClasses(SB), NOSPLIT, $0
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MOVV R4, F5
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MOVV F6, R7
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MOVW R8, F9
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MOVW F10, R11
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MOVV R12, FCC0
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MOVV FCC1, R13
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MOVV R14, FCSR0
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MOVV FCSR3, R15
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FSEL FCC0, F3, F4, F3
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FSEL FCC1, F1, F2
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RET
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TEXT ·memOffsets(SB), NOSPLIT, $0
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MOVB 2047(R4), R5
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MOVB -2048(R4), R5
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MOVH 2047(R4), R5
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MOVW 2047(R4), R5
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MOVV 2047(R4), R5
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MOVW 2048(R4), R5
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MOVW -2048(R4), R5
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MOVW 4095(R4), R5
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MOVW -4096(R4), R5
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MOVW 65536(R4), R5
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MOVW $4(R4), R5
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MOVV $4(R4), R5
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MOVBU -1(R4), R5
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MOVHU 2(R4), R5
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MOVWU -3(R4), R5
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MOVF 8(R4), F5
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MOVD -8(R4), F5
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MOVV (R4)(R5), R6
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RET
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+61
@@ -0,0 +1,61 @@
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
// Seed corpus for FuzzAssembleLOONG64: the shuffle/permute immediate family.
|
||||
// VSHUF4I.B/H/W take a ui8 packing two position nibbles; VSHUF4I.V is
|
||||
// range-gated to 0..15 although its field is ui8, the same gate the
|
||||
// toolchain keeps. VPERMI.W and the VEXTRINS pack an element index and an
|
||||
// insert/extract order in one ui8.
|
||||
|
||||
#include "textflag.h"
|
||||
|
||||
TEXT ·shuf4(SB), NOSPLIT, $0
|
||||
VSHUF4IB $0, V2, V1
|
||||
VSHUF4IB $16, V2, V1
|
||||
VSHUF4IB $255, V2, V1
|
||||
VSHUF4IH $0, V2, V1
|
||||
VSHUF4IH $128, V2, V1
|
||||
VSHUF4IH $255, V2, V1
|
||||
VSHUF4IW $0, V2, V1
|
||||
VSHUF4IW $96, V2, V1
|
||||
VSHUF4IW $255, V2, V1
|
||||
VSHUF4IV $0, V2, V1
|
||||
VSHUF4IV $8, V2, V1
|
||||
VSHUF4IV $15, V2, V1
|
||||
RET
|
||||
|
||||
TEXT ·shuf4X(SB), NOSPLIT, $0
|
||||
XVSHUF4IB $0, X2, X1
|
||||
XVSHUF4IB $255, X2, X1
|
||||
XVSHUF4IH $255, X2, X1
|
||||
XVSHUF4IW $255, X2, X1
|
||||
XVSHUF4IV $0, X2, X1
|
||||
XVSHUF4IV $15, X2, X1
|
||||
RET
|
||||
|
||||
TEXT ·permi(SB), NOSPLIT, $0
|
||||
VPERMIW $0, V2, V1
|
||||
VPERMIW $255, V2, V1
|
||||
XVPERMIW $0, X2, X1
|
||||
XVPERMIW $255, X2, X1
|
||||
XVPERMIV $0, X2, X1
|
||||
XVPERMIV $255, X2, X1
|
||||
XVPERMIQ $0, X2, X1
|
||||
XVPERMIQ $255, X2, X1
|
||||
RET
|
||||
|
||||
TEXT ·extrins(SB), NOSPLIT, $0
|
||||
VEXTRINSB $0, V2, V1
|
||||
VEXTRINSB $255, V2, V1
|
||||
VEXTRINSH $0, V2, V1
|
||||
VEXTRINSH $255, V2, V1
|
||||
VEXTRINSW $0, V2, V1
|
||||
VEXTRINSW $255, V2, V1
|
||||
VEXTRINSV $0, V2, V1
|
||||
VEXTRINSV $255, V2, V1
|
||||
XVEXTRINSB $0, X2, X1
|
||||
XVEXTRINSB $255, X2, X1
|
||||
XVEXTRINSH $255, X2, X1
|
||||
XVEXTRINSW $255, X2, X1
|
||||
XVEXTRINSV $255, X2, X1
|
||||
RET
|
||||
Reference in new issue
Block a user