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test(asm): seed the riscv64 and loong64 assemble fuzz targets

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Assisted-by: GLM 5.3
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petrbalvin committed 2026-10-07 13:51:02 +02:00
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commit 965b33e5b0
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asm/testdata/seeds/loong64/llsc-offsets.s
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause
// Seed corpus for FuzzAssembleLOONG64: the ll/sc and pointer load/store
// offset ladder, the three spans the encoder classifies by (a signed 16-bit
// offset alone, a 32-bit one split through addu16i.d into R30, a wider one
// materialised in full), the acquire/release pair, sc.q and the atomics with
// their dbar forms.
#include "textflag.h"
TEXT ·llscNear(SB), NOSPLIT, $0
LL (R12), R13
LL 0(R12), R13
LL 4(R12), R13
LLW 8(R12), R13
LLW -4(R12), R13
LLV 8(R14), R15
LLV -8(R14), R15
SC R16, (R17)
SC R16, 0(R17)
SCW R16, 4(R17)
SCV R18,-8(R19)
RET
TEXT ·llscSpans(SB), NOSPLIT, $0
LL 1020(R12), R13
LL 1024(R12), R13
LL -1024(R12), R13
LLW 32760(R12), R13
LLW 32764(R12), R13
LLW 32768(R12), R13
LLW -32768(R12), R13
LLV 65532(R14), R15
LLV 65536(R14), R15
LLV 131068(R14), R15
LLW 1048572(R12), R13
LLV 2147483644(R14), R15
LLV -2147483648(R14), R15
SC R16, 1020(R17)
SCW R16, 32764(R17)
SCV R18, 65532(R19)
SCV R18, 65536(R19)
RET
TEXT ·ptrForms(SB), NOSPLIT, $0
MOVWP R16, (R17)
MOVWP R16, 8(R17)
MOVVP R18, (R19)
MOVVP R18,-8(R19)
RET
TEXT ·acqRel(SB), NOSPLIT, $0
LLACQW (R5), R4
LLACQV (R5), R4
SCRELW R4, (R6)
SCRELV R4, (R6)
SCQ R4, R5, (R6)
RET
TEXT ·atomics(SB), NOSPLIT, $0
AMSWAPB R14, (R13), R12
AMSWAPH R14, (R13), R12
AMSWAPW R14, (R13), R12
AMSWAPV R14, (R13), R12
AMCASB R14, (R13), R12
AMCASDBV R14, (R13), R12
AMADDW R14, (R13), R12
AMADDV R14, (R13), R12
AMANDW R6, (R5), R4
AMORW R0, (R5), R4
AMXORV R14, (R13), R12
AMMAXW R14, (R13), R12
AMMINV R14, (R13), R12
AMMAXWU R14, (R13), R12
AMMINVU R14, (R13), R12
AMADDDBW R14, (R13), R12
AMADDDBV R14, (R13), R12
AMANDDBW R6, (R5), R4
AMORDBV R14, (R13), R12
AMXORDBW R14, (R13), R12
AMMAXDBWU R14, (R13), R12
AMMINDBVU R14, (R13), R12
RET