test(asm): seed the riscv64 and loong64 assemble fuzz targets
Assisted-by: GLM 5.3
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+35
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Seed corpus for FuzzAssembleRISCV64: the CSR instructions over the whole
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// 12-bit address range and the 5-bit immediate window of the CSRRWI family.
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#include "textflag.h"
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TEXT ·csrRegs(SB), NOSPLIT, $0
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CSRRW $0x300, X5, X6
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CSRRS $0x304, X7, X8
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CSRRC $0x305, X9, X10
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CSRRW $0, X5, X6
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CSRRS $0xFFF, X7, X8
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CSRRC $0x7FF, X9, X10
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CSRRW $0x341, X0, X6
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CSRRS $0x342, X0, X6
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RET
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TEXT ·csrImm(SB), NOSPLIT, $0
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CSRRWI $0x300, $0, X6
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CSRRSI $0x304, $31, X8
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CSRRCI $0x305, $1, X10
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CSRRWI $0xFFF, $15, X6
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CSRRSI $0, $31, X8
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CSRRCI $0x7FF, $16, X10
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RET
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TEXT ·csrNamed(SB), NOSPLIT, $0
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CSRRS $0xC00, X0, X14
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CSRRS $0xC01, X0, X15
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CSRRS $0xC02, X0, X16
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CSRRW $0x105, X5, X6
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CSRRSI $0x106, $1, X7
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RET
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+106
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Seed corpus for FuzzAssembleRISCV64: the immediate-range ladder of the
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// I-type arithmetic and the U-type pair, the family GOROOT's riscv64
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// assembler corpus walks (cmd/asm/internal/asm/testdata/riscv64.s). Every
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// boundary sits on an encoder gate: the 12-bit signed window, the
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// one-instruction and two-instruction decompositions, the shamt widths and
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// the wide MOV immediate that goes through the literal pool.
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#include "textflag.h"
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TEXT ·immIType(SB), NOSPLIT, $0
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ADDI $2047, X5, X6
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ADDI $-2048, X5, X6
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ADDI $2048, X5, X6
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ADDI $-2049, X5, X6
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ADDI $4094, X5, X6
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ADDI $-4096, X5, X6
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ADDI $4095, X5, X6
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ADDI $-4097, X5, X6
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ADDI $0, X5, X6
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SLTI $2047, X5, X7
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SLTI $-2048, X5, X7
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SLTIU $2047, X5, X7
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SLTIU $-2048, X5, X7
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ANDI $-2048, X5, X6
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ANDI $2047, X5, X6
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ORI $-1, X5, X6
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XORI $2047, X5, X6
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XORI $-2048, X5, X6
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RET
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TEXT ·immAlias(SB), NOSPLIT, $0
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ADD $2047, X5, X6
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ADD $2048, X5, X6
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SUB $1, X5, X6
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SUB $2049, X5, X6
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AND $-1, X5, X6
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OR $2047, X5, X6
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XOR $-2048, X5, X6
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SLT $55, X5, X7
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SLTU $55, X5, X7
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ADDW $2047, X5, X6
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RET
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TEXT ·immUType(SB), NOSPLIT, $0
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LUI $0x7FFFF, X6
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LUI $-0x80000, X6
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LUI $1, X6
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AUIPC $0x7FFFF, X7
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AUIPC $-0x80000, X7
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RET
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TEXT ·immShift(SB), NOSPLIT, $0
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SLLI $0, X5, X6
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SLLI $31, X5, X6
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SLLI $63, X5, X6
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SRLI $31, X5, X6
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SRLI $63, X5, X6
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SRAI $1, X5, X6
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SRAI $63, X5, X6
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SLLIW $31, X5, X6
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SRLIW $31, X5, X6
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SRAIW $31, X5, X6
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SLLIUW $31, X5, X6
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RET
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TEXT ·immWide(SB), NOSPLIT, $0
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MOV $0, X10
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MOV $2047, X10
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MOV $2048, X10
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MOV $-2048, X10
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MOV $4095, X10
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MOV $-4097, X10
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MOV $0x12345678, X10
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MOV $0x123456789, X10
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MOV $0x123456789ABCDEF0, X10
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MOV $-1, X11
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MOV $-0x8000000000000000, X11
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MOV $0x7FFFFFFFFFFFFFFF, X12
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RET
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TEXT ·memOffsets(SB), NOSPLIT, $0
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LD 0(X10), X11
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LD 2047(X10), X11
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LD -2048(X10), X11
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LD 2048(X10), X11
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LD 4095(X10), X11
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LD -4096(X10), X11
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LW 0(X10), X12
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LBU -1(X10), X12
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LHU 2(X10), X12
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LWU -3(X10), X12
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SD X11, 0(X10)
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SD X11, 2047(X10)
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SD X11,-2048(X10)
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SD X11, 4095(X10)
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SW X12,-4096(X10)
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SH X12, 6(X10)
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SB X12, 7(X10)
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FLW 8(X10), F8
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FLD -8(X10), F8
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FSW F8, 16(X10)
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FSD F8,-16(X10)
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RET
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Vendored
+95
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Seed corpus for FuzzAssembleRISCV64: the RVC-compressible shapes. Every
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// instruction here has a compressed 16-bit encoding the compression pass may
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// pick: the two-operand ALU forms over x8-x15, the stack-pointer loads and
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// stores at the scaled offset boundaries, C.ADDI16SP and C.ADDI4SPN ranges,
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// the compressed branches and the uncompressible spellings beside them.
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#include "textflag.h"
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TEXT ·primeALU(SB), NOSPLIT, $0
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ADD X9, X8, X8
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ADD X15, X8, X8
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ADDI $1, X8, X8
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ADDI $31, X15, X15
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ADDI $-32, X8, X8
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AND X9, X8, X8
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ANDI $3, X8, X8
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OR X10, X9, X9
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XOR X11, X10, X10
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SUB X13, X12, X12
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SLLI $2, X8, X8
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SRLI $5, X9, X9
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SRAI $7, X10, X10
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MOV X9, X8
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MOV X1, X8
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MOV X8, X1
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RET
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TEXT ·stackOffsets(SB), NOSPLIT, $0
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LW 0(X2), X8
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LW 4(X2), X8
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LW 124(X2), X9
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LW 2044(X2), X10
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LD 0(X2), X8
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LD 8(X2), X8
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LD 504(X2), X9
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SW X8, 0(X2)
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SW X8, 124(X2)
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SW X8, 2044(X2)
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SD X8, 0(X2)
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SD X8, 504(X2)
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FLW 0(X2), F8
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FLD 504(X2), F8
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FSW F8, 0(X2)
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FSD F8, 504(X2)
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RET
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TEXT ·frameAdj(SB), NOSPLIT, $0
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ADDI $16, X2, X2
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ADDI $-16, X2, X2
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ADDI $496, X2, X2
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ADDI $-512, X2, X2
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ADDI $1024, X2, X2
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ADDI $2048, X2, X2
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ADDI $1, X2, X2
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RET
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TEXT ·primeMem(SB), NOSPLIT, $0
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LW 0(X8), X9
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LW 4(X8), X10
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LW 124(X8), X11
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LD 0(X8), X9
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LD 8(X8), X10
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LD 120(X8), X11
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SW X9, 0(X8)
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SW X9, 124(X8)
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SD X9, 0(X8)
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SD X9, 120(X8)
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RET
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TEXT ·cBranches(SB), NOSPLIT, $0
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BEQ X8, X0, cb1
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BNE X9, X0, cb2
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BLT X10, X0, cb1
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BGE X11, X0, cb2
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BLTU X12, X0, cb1
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BGEU X13, X0, cb2
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cb1:
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MOV X8, X9
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cb2:
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MOV X9, X8
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RET
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TEXT ·uncompressible(SB), NOSPLIT, $0
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ADD X17, X16, X16
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ADDI $2048, X8, X8
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LW 2048(X2), X10
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LD 512(X2), X10
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SW X8, 2048(X2)
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ADDI $2049, X2, X2
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RET
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Vendored
+233
@@ -0,0 +1,233 @@
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Seed corpus for FuzzAssembleRISCV64: the RVV surface. The configuration
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// setters, the load/store families with their segment and fault-only-first
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// variants, the arithmetic operand classes (VV/VX/VI, the masks, the
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// merge and carry forms, the reductions and the whole-register moves).
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#include "textflag.h"
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TEXT ·config(SB), NOSPLIT, $0
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VSETVLI X5, E8, M8, TA, MA, X6
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VSETVLI X5, E8, M1, TU, MU, X6
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VSETVLI $15, E32, M1, TA, MA, X12
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VSETVLI $31, E64, M2, TU, MU, X12
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VSETIVLI $0, E16, M4, TA, MA, X0
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VSETIVLI $4, E32, M1, TA, MA, X0
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VSETIVLI $31, E8, M8, TU, MU, X15
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RET
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TEXT ·loads(SB), NOSPLIT, $0
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VLE8V (X10), V8
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VLE16V (X10), V8
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VLE32V (X10), V8
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VLE64V (X11), V16
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VSE8V V8, (X10)
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VSE16V V8, (X10)
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VSE32V V15, (X11)
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VSE64V V24, (X10)
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VLSE8V (X14), X9, V0
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VLSE32V (X14), X5, V4
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VSSE64V V4, X7, (X14)
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VLUXEI8V (X10), V20, V4
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VLOXEI32V (X10), V20, V4
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VSUXEI64V V4, V20, (X10)
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VSOXEI16V V4, V20, (X10)
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VLE8FFV (X10), V8
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RET
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TEXT ·segments(SB), NOSPLIT, $0
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VLSEG2E8V (X14), V0
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VLSEG4E32V (X14), V0
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VLSEG8E64V (X14), V4
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VSSEG2E32V V0, (X14)
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VSSEG8E8V V4, (X14)
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VLSSEG4E32V (X14), X0, V0
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VLSSEG8E32V (X10), X0, V4
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VLUXSEG2EI32V (X10), V20, V4
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VLOXSEG4EI64V (X10), V20, V4
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VSUXSEG2EI8V V4, V20, (X10)
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VLSEG4E8FFV (X14), V0
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RET
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TEXT ·wholeReg(SB), NOSPLIT, $0
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VL1RV (X10), V8
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VL2RV (X10), V16
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VL4RV (X10), V0
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VL8RV (X10), V0
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VS1RV V8, (X10)
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VS2RV V16, (X10)
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VS4RV V0, (X10)
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VS8RV V0, (X10)
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VL1RE8V (X10), V8
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VL2RE16V (X10), V16
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VL4RE32V (X10), V0
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VL8RE64V (X10), V0
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VL2RE64V (X10), V16
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VLMV (X10), V0
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VSMV V0, (X10)
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RET
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TEXT ·arith(SB), NOSPLIT, $0
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VADDVV V1, V2, V3
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VADDVV V1, V2, V0, V3
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VADDVX X10, V2, V0, V3
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VADDVI $15, V2, V0, V3
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VADDVI $-16, V2, V0, V3
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VADDVI $0, V2, V3
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VSUBVV V1, V2, V0, V3
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VSUBVX X10, V2, V3
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VRSUBVX X10, V2, V0, V3
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VRSUBVI $15, V2, V0, V3
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VANDVI $-1, V2, V3
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VORVI $15, V2, V3
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VORVI $-16, V2, V3
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VXORVI $0, V2, V3
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VNEGV V2, V0, V3
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VNOTV V2, V3
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VIDV V12
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VFMVVF F10, V14
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VMVVI $15, V14
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VMVVI $-16, V14
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VMVVV V1, V4
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VMVVX X10, V4
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VMVXS V4, X10
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VFMVSF F10, X11
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RET
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TEXT ·shiftsSliding(SB), NOSPLIT, $0
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VSLLVI $0, V28, V30
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VSLLVI $31, V28, V30
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VSRLVI $25, V29, V29
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VSRAVI $31, V4, V5
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VNSRLWI $31, V6, V7
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VNSRAWI $0, V6, V7
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VSLLVV V1, V2, V3
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VSRLVX X10, V2, V3
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VSRAVV V1, V2, V3
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VRORVI $7, V4, V5
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VRORVI $31, V4, V5
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VRORVV V1, V2, V3
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VROLVX X10, V2, V3
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VSLIDEUPVI $31, V4, V5
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VSLIDEUPVX X10, V4, V5
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VSLIDEDOWNVI $0, V4, V5
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VSLIDEDOWNVX X10, V4, V5
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VFSLIDE1UPVF F10, V4, V5
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VFSLIDE1DOWNVF F10, V4, V5
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VRGATHERVI $31, V2, V3
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VRGATHERVV V1, V2, V3
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VRGATHERVX X10, V2, V3
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RET
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TEXT ·compareMask(SB), NOSPLIT, $0
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VMSEQVV V1, V2, V0
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VMSEQVX X10, V2, V0
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VMSEQVI $0, V2, V0
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VMSNEVI $-16, V2, V0
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VMSLTVI $15, V2, V0
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VMSLTUVI $15, V2, V0
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VMSLEVI $-1, V2, V0
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VMSGEVI $15, V2, V0
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VMSGEUVI $0, V2, V0
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VMSGTVV V1, V2, V0
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VMSLEVV V1, V2, V0
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VMFEQVF F10, V2, V0
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VMFLTVF F10, V2, V0
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VMFGEVF F10, V2, V0
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VMANDMM V1, V2, V3
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VMNANDMM V1, V2, V3
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VMANDNMM V1, V2, V3
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VMORMM V1, V2, V3
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VMXORMM V1, V2, V3
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VMXNORMM V1, V2, V3
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VMNORMM V1, V2, V3
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VMORNMM V1, V2, V3
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VMCLRM V1
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VMSETM V1
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VMNOTM V1, V2
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VCPOPM V0, X6
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VFIRSTM V0, X7
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VIOTAM V0, X5
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VMSBFM V0, V1
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VMSIFM V0, V1
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VMSOFM V0, V1
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RET
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TEXT ·carryMerge(SB), NOSPLIT, $0
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VADCVVM V1, V2, V0, V3
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VADCVXM X10, V2, V0, V3
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VADCVIM $15, V2, V0, V3
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VMADCVV V1, V2, V3
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VMADCVX X10, V2, V3
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VMADCVI $-16, V2, V3
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VSBCVVM V1, V2, V0, V3
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VSBCVXM X10, V2, V0, V3
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VSBCVVM V1, V2, V0, V3
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VSBCVXM X10, V2, V0, V3
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VMADCVV V1, V2, V3
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VMADCVX X10, V2, V3
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VMADCVI $0, V2, V3
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VMADCVVM V1, V2, V0, V3
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VMERGEVVM V1, V2, V0, V3
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VMERGEVXM X10, V2, V0, V3
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VMERGEVIM $15, V2, V0, V3
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VFMERGEVFM F10, V2, V0, V3
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RET
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TEXT ·reduceWiden(SB), NOSPLIT, $0
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VREDSUMVS V1, V2, V3
|
||||
VREDMAXUVS V1, V2, V3
|
||||
VREDMINVS V1, V2, V3
|
||||
VREDANDVS V1, V2, V3
|
||||
VREDORVS V1, V2, V3
|
||||
VREDXORVS V1, V2, V3
|
||||
VWREDSUMUVS V1, V2, V3
|
||||
VWREDSUMVS V1, V2, V3
|
||||
VFWREDOSUMVS V1, V2, V3
|
||||
VFWREDUSUMVS V1, V2, V3
|
||||
VWADDUVV V1, V2, V3
|
||||
VWADDWV V1, V2, V3
|
||||
VWSUBUVV V1, V2, V3
|
||||
VWSUBWV V1, V2, V3
|
||||
VWADDUWX X10, V2, V3
|
||||
VWADDWX X10, V2, V3
|
||||
VMULVV V1, V2, V3
|
||||
VMULHUVV V1, V2, V3
|
||||
VMULHSUVV V1, V2, V3
|
||||
VDIVUVV V1, V2, V3
|
||||
VREMVV V1, V2, V3
|
||||
VSMULVV V1, V2, V3
|
||||
VCLMULVV V1, V2, V3
|
||||
VCLMULHVX X10, V2, V3
|
||||
RET
|
||||
|
||||
TEXT ·fpVec(SB), NOSPLIT, $0
|
||||
VFADDVV V1, V2, V3
|
||||
VFADDVF F10, V2, V3
|
||||
VFSUBVF F10, V2, V3
|
||||
VFMULVV V1, V2, V3
|
||||
VFDIVVF F10, V2, V3
|
||||
VFRSUBVF F10, V2, V3
|
||||
VFMINVV V1, V2, V3
|
||||
VFMAXVF F10, V2, V3
|
||||
VFMACCVV V1, V2, V3
|
||||
VFMACCVF F10, V2, V3
|
||||
VFMSACVV V1, V2, V3
|
||||
VFNMSACVF F10, V2, V3
|
||||
VFMADDVV V1, V2, V3
|
||||
VFNMADDVF F10, V2, V3
|
||||
VFWMACCVV V1, V2, V3
|
||||
VFWMSACVF F10, V2, V3
|
||||
VFSQRTV V4, V5
|
||||
VFCLASSV V4, V5
|
||||
VFREC7V V4, V5
|
||||
VFRSQRT7V V4, V5
|
||||
VFCVTXFV V4, V5
|
||||
VFCVTRTZXFV V4, V5
|
||||
VFNCVTFFW V4, V5
|
||||
VFWCVTFFV V4, V5
|
||||
VSEXTVF2 V4, V5
|
||||
VZEXTVF8 V4, V5
|
||||
RET
|
||||
+177
@@ -0,0 +1,177 @@
|
||||
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
// Seed corpus for FuzzAssembleRISCV64: branches over their offset range, the
|
||||
// jumps and calls, the system instructions, the atomics with the LR/SC pair,
|
||||
// the FP arithmetic, compare, conversion and fused multiply-add families in
|
||||
// every width including quad.
|
||||
|
||||
#include "textflag.h"
|
||||
|
||||
TEXT ·branches(SB), NOSPLIT, $0
|
||||
BEQ X5, X6, b1
|
||||
BNE X5, X6, b2
|
||||
BLT X5, X6, b1
|
||||
BGE X5, X6, b2
|
||||
BLTU X5, X6, b1
|
||||
BGEU X5, X6, b2
|
||||
BGT X6, X5, b1
|
||||
BLE X6, X5, b2
|
||||
BGTU X6, X5, b1
|
||||
BLEU X6, X5, b2
|
||||
|
||||
b1:
|
||||
ADDI $1, X5, X5
|
||||
|
||||
b2:
|
||||
ADDI $-1, X6, X6
|
||||
BEQ X5, X6, b1
|
||||
RET
|
||||
|
||||
TEXT ·farBranch(SB), NOSPLIT, $0
|
||||
BEQ X5, X6, far
|
||||
SLTI $2047, X5, X6
|
||||
BEQ X5, X6, far
|
||||
|
||||
far:
|
||||
SLTIU $2047, X5, X6
|
||||
BGE X5, X6, far
|
||||
RET
|
||||
|
||||
TEXT ·jumps(SB), NOSPLIT, $0
|
||||
JAL X1, j1
|
||||
|
||||
j1:
|
||||
JALR X0, (X1)
|
||||
JALR X1, 0(X5)
|
||||
JMP j2
|
||||
|
||||
j2:
|
||||
JMP (X5)
|
||||
CALL (X5)
|
||||
JMP -3(PC)
|
||||
CALL runtime·morestack_noctxt(SB)
|
||||
RET
|
||||
|
||||
TEXT ·system(SB), NOSPLIT, $0
|
||||
FENCE
|
||||
FENCE.TSO
|
||||
PAUSE
|
||||
ECALL
|
||||
EBREAK
|
||||
RET
|
||||
|
||||
TEXT ·atomics(SB), NOSPLIT, $0
|
||||
AMOSWAPW X5, (X6), X7
|
||||
AMOSWAPD X5, (X6), X7
|
||||
AMOADDW X5, (X6), X7
|
||||
AMOADDD X5, (X6), X7
|
||||
AMOANDW X5, (X6), X7
|
||||
AMOORW X5, (X6), X7
|
||||
AMOXORW X5, (X6), X7
|
||||
AMOMINW X5, (X6), X7
|
||||
AMOMAXW X5, (X6), X7
|
||||
AMOMINUW X5, (X6), X7
|
||||
AMOMAXUW X5, (X6), X7
|
||||
AMOMIND X5, (X6), X7
|
||||
AMOMAXD X5, (X6), X7
|
||||
AMOMINUD X5, (X6), X7
|
||||
AMOMAXUD X5, (X6), X7
|
||||
LRW (X6), X7
|
||||
LRD (X6), X7
|
||||
SCW X5, (X6), X7
|
||||
SCD X5, (X6), X7
|
||||
RET
|
||||
|
||||
TEXT ·fpArith(SB), NOSPLIT, $0
|
||||
FADDS F1, F2, F3
|
||||
FSUBS F1, F2, F3
|
||||
FMULS F1, F2, F3
|
||||
FDIVS F1, F2, F3
|
||||
FADDD F1, F2, F3
|
||||
FSUBD F1, F2, F3
|
||||
FMULD F1, F2, F3
|
||||
FDIVD F1, F2, F3
|
||||
FADDQ F1, F2, F3
|
||||
FSUBQ F1, F2, F3
|
||||
FMULQ F1, F2, F3
|
||||
FDIVQ F1, F2, F3
|
||||
FSQRTS F1, F2
|
||||
FSQRTD F1, F2
|
||||
FSQRTQ F1, F2
|
||||
FMINS F1, F2, F3
|
||||
FMAXS F1, F2, F3
|
||||
FMIND F1, F2, F3
|
||||
FMAXD F1, F2, F3
|
||||
FMINQ F1, F2, F3
|
||||
FMAXQ F1, F2, F3
|
||||
RET
|
||||
|
||||
TEXT ·fpFma(SB), NOSPLIT, $0
|
||||
FMADDS F1, F2, F3, F4
|
||||
FMSUBS F1, F2, F3, F4
|
||||
FNMSUBS F1, F2, F3, F4
|
||||
FNMADDS F1, F2, F3, F4
|
||||
FMADDD F1, F2, F3, F4
|
||||
FMSUBD F1, F2, F3, F4
|
||||
FNMSUBD F1, F2, F3, F4
|
||||
FNMADDD F1, F2, F3, F4
|
||||
FMADDQ F1, F2, F3, F4
|
||||
FMSUBQ F1, F2, F3, F4
|
||||
FNMSUBQ F1, F2, F3, F4
|
||||
FNMADDQ F1, F2, F3, F4
|
||||
RET
|
||||
|
||||
TEXT ·fpCvt(SB), NOSPLIT, $0
|
||||
FCVTWS F1, X5
|
||||
FCVTWUS F1, X5
|
||||
FCVTLS F1, X5
|
||||
FCVTLUS F1, X5
|
||||
FCVTWD F1, X5
|
||||
FCVTWUD F1, X5
|
||||
FCVTLD F1, X5
|
||||
FCVTLUD F1, X5
|
||||
FCVTSW X5, F1
|
||||
FCVTSWU X5, F1
|
||||
FCVTSL X5, F1
|
||||
FCVTSLU X5, F1
|
||||
FCVTDW X5, F1
|
||||
FCVTDWU X5, F1
|
||||
FCVTDL X5, F1
|
||||
FCVTDLU X5, F1
|
||||
FCVTSD F1, F2
|
||||
FCVTDS F1, F2
|
||||
FCVTSQ F1, F2
|
||||
FCVTDQ F1, F2
|
||||
FCVTQS F1, F2
|
||||
FCVTQD F1, F2
|
||||
FCVTWQ F1, X5
|
||||
FCVTLQ F1, X5
|
||||
FCVTQW X5, F1
|
||||
FCVTQL X5, F1
|
||||
FCLASSS F1, X5
|
||||
FCLASSD F1, X5
|
||||
FCLASSQ F1, X5
|
||||
FMVXD F1, X5
|
||||
FMVDX X5, F1
|
||||
FMVXW F1, X5
|
||||
FMVWX X5, F1
|
||||
RET
|
||||
|
||||
TEXT ·fpSign(SB), NOSPLIT, $0
|
||||
FSGNJS F1, F0, F2
|
||||
FSGNJNS F1, F0, F2
|
||||
FSGNJXS F1, F0, F2
|
||||
FSGNJD F1, F0, F2
|
||||
FSGNJND F1, F0, F2
|
||||
FSGNJXD F1, F0, F2
|
||||
FLTS F1, F2, X5
|
||||
FLES F1, F2, X5
|
||||
FEQS F1, F2, X5
|
||||
FLTD F1, F2, X5
|
||||
FLED F1, F2, X5
|
||||
FEQD F1, F2, X5
|
||||
FLTQ F1, F2, X5
|
||||
FLEQ F1, F2, X5
|
||||
FEQQ F1, F2, X5
|
||||
RET
|
||||
Vendored
+65
@@ -0,0 +1,65 @@
|
||||
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
// Seed corpus for FuzzAssembleRISCV64: the Zbb/Zba/Zbs/Zicond bit-manipulation
|
||||
// and address-generation set, with every unary form's W variant and the
|
||||
// shamt-range immediate forms.
|
||||
|
||||
#include "textflag.h"
|
||||
|
||||
TEXT ·unary(SB), NOSPLIT, $0
|
||||
CLZ X5, X6
|
||||
CLZW X5, X6
|
||||
CTZ X5, X6
|
||||
CTZW X5, X6
|
||||
CPOP X5, X6
|
||||
CPOPW X5, X6
|
||||
SEXTB X5, X6
|
||||
SEXTH X5, X6
|
||||
ZEXTH X5, X6
|
||||
ORCB X5, X6
|
||||
REV8 X5, X6
|
||||
RET
|
||||
|
||||
TEXT ·rolRor(SB), NOSPLIT, $0
|
||||
ROL X7, X5, X6
|
||||
ROR X7, X5, X6
|
||||
RORI $0, X5, X6
|
||||
RORI $63, X5, X6
|
||||
ANDN X7, X5, X6
|
||||
ORN X7, X5, X6
|
||||
XNOR X7, X5, X6
|
||||
MAX X7, X5, X6
|
||||
MAXU X7, X5, X6
|
||||
MIN X7, X5, X6
|
||||
MINU X7, X5, X6
|
||||
CLMUL X7, X5, X6
|
||||
CLMULH X7, X5, X6
|
||||
CLMULR X7, X5, X6
|
||||
RET
|
||||
|
||||
TEXT ·addrGen(SB), NOSPLIT, $0
|
||||
SH1ADD X7, X5, X6
|
||||
SH2ADD X7, X5, X6
|
||||
SH3ADD X7, X5, X6
|
||||
SH1ADDUW X7, X5, X6
|
||||
SH2ADDUW X7, X5, X6
|
||||
SH3ADDUW X7, X5, X6
|
||||
ADDUW X7, X5, X6
|
||||
RET
|
||||
|
||||
TEXT ·bitImm(SB), NOSPLIT, $0
|
||||
BCLR $31, X5, X6
|
||||
BEXT $63, X5, X6
|
||||
BINV $0, X5, X6
|
||||
BSET $31, X5, X6
|
||||
BCLRI $63, X5, X6
|
||||
BEXTI $31, X5, X6
|
||||
BINVI $63, X5, X6
|
||||
BSETI $63, X5, X6
|
||||
RET
|
||||
|
||||
TEXT ·condZero(SB), NOSPLIT, $0
|
||||
CZEROEQZ X7, X5, X6
|
||||
CZERONEZ X7, X5, X6
|
||||
RET
|
||||
Reference in new issue
Block a user