test(asm): seed the riscv64 and loong64 assemble fuzz targets

Assisted-by: GLM 5.3

asm/testdata/seeds/riscv64/csr.s

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+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+// Seed corpus for FuzzAssembleRISCV64: the CSR instructions over the whole
+// 12-bit address range and the 5-bit immediate window of the CSRRWI family.
+
+#include "textflag.h"
+
+TEXT ·csrRegs(SB), NOSPLIT, $0
+	CSRRW $0x300, X5, X6
+	CSRRS $0x304, X7, X8
+	CSRRC $0x305, X9, X10
+	CSRRW $0, X5, X6
+	CSRRS $0xFFF, X7, X8
+	CSRRC $0x7FF, X9, X10
+	CSRRW $0x341, X0, X6
+	CSRRS $0x342, X0, X6
+	RET
+
+TEXT ·csrImm(SB), NOSPLIT, $0
+	CSRRWI $0x300, $0, X6
+	CSRRSI $0x304, $31, X8
+	CSRRCI $0x305, $1, X10
+	CSRRWI $0xFFF, $15, X6
+	CSRRSI $0, $31, X8
+	CSRRCI $0x7FF, $16, X10
+	RET
+
+TEXT ·csrNamed(SB), NOSPLIT, $0
+	CSRRS  $0xC00, X0, X14
+	CSRRS  $0xC01, X0, X15
+	CSRRS  $0xC02, X0, X16
+	CSRRW  $0x105, X5, X6
+	CSRRSI $0x106, $1, X7
+	RET