test(asm): seed the riscv64 and loong64 assemble fuzz targets

Assisted-by: GLM 5.3

asm/testdata/seeds/riscv64/imm-ranges.s

@@ -0,0 +1,106 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+// Seed corpus for FuzzAssembleRISCV64: the immediate-range ladder of the
+// I-type arithmetic and the U-type pair, the family GOROOT's riscv64
+// assembler corpus walks (cmd/asm/internal/asm/testdata/riscv64.s).  Every
+// boundary sits on an encoder gate: the 12-bit signed window, the
+// one-instruction and two-instruction decompositions, the shamt widths and
+// the wide MOV immediate that goes through the literal pool.
+
+#include "textflag.h"
+
+TEXT ·immIType(SB), NOSPLIT, $0
+	ADDI  $2047, X5, X6
+	ADDI  $-2048, X5, X6
+	ADDI  $2048, X5, X6
+	ADDI  $-2049, X5, X6
+	ADDI  $4094, X5, X6
+	ADDI  $-4096, X5, X6
+	ADDI  $4095, X5, X6
+	ADDI  $-4097, X5, X6
+	ADDI  $0, X5, X6
+	SLTI  $2047, X5, X7
+	SLTI  $-2048, X5, X7
+	SLTIU $2047, X5, X7
+	SLTIU $-2048, X5, X7
+	ANDI  $-2048, X5, X6
+	ANDI  $2047, X5, X6
+	ORI   $-1, X5, X6
+	XORI  $2047, X5, X6
+	XORI  $-2048, X5, X6
+	RET
+
+TEXT ·immAlias(SB), NOSPLIT, $0
+	ADD  $2047, X5, X6
+	ADD  $2048, X5, X6
+	SUB  $1, X5, X6
+	SUB  $2049, X5, X6
+	AND  $-1, X5, X6
+	OR   $2047, X5, X6
+	XOR  $-2048, X5, X6
+	SLT  $55, X5, X7
+	SLTU $55, X5, X7
+	ADDW $2047, X5, X6
+	RET
+
+TEXT ·immUType(SB), NOSPLIT, $0
+	LUI   $0x7FFFF, X6
+	LUI   $-0x80000, X6
+	LUI   $1, X6
+	AUIPC $0x7FFFF, X7
+	AUIPC $-0x80000, X7
+	RET
+
+TEXT ·immShift(SB), NOSPLIT, $0
+	SLLI   $0, X5, X6
+	SLLI   $31, X5, X6
+	SLLI   $63, X5, X6
+	SRLI   $31, X5, X6
+	SRLI   $63, X5, X6
+	SRAI   $1, X5, X6
+	SRAI   $63, X5, X6
+	SLLIW  $31, X5, X6
+	SRLIW  $31, X5, X6
+	SRAIW  $31, X5, X6
+	SLLIUW $31, X5, X6
+	RET
+
+TEXT ·immWide(SB), NOSPLIT, $0
+	MOV $0, X10
+	MOV $2047, X10
+	MOV $2048, X10
+	MOV $-2048, X10
+	MOV $4095, X10
+	MOV $-4097, X10
+	MOV $0x12345678, X10
+	MOV $0x123456789, X10
+	MOV $0x123456789ABCDEF0, X10
+	MOV $-1, X11
+	MOV $-0x8000000000000000, X11
+	MOV $0x7FFFFFFFFFFFFFFF, X12
+	RET
+
+TEXT ·memOffsets(SB), NOSPLIT, $0
+	LD  0(X10), X11
+	LD  2047(X10), X11
+	LD  -2048(X10), X11
+	LD  2048(X10), X11
+	LD  4095(X10), X11
+	LD  -4096(X10), X11
+	LW  0(X10), X12
+	LBU -1(X10), X12
+	LHU 2(X10), X12
+	LWU -3(X10), X12
+	SD  X11, 0(X10)
+	SD  X11, 2047(X10)
+	SD  X11,-2048(X10)
+	SD  X11, 4095(X10)
+	SW  X12,-4096(X10)
+	SH  X12, 6(X10)
+	SB  X12, 7(X10)
+	FLW 8(X10), F8
+	FLD -8(X10), F8
+	FSW F8, 16(X10)
+	FSD F8,-16(X10)
+	RET