test(asm): seed the riscv64 and loong64 assemble fuzz targets

Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
1 parent b9dfb48d79
commit 965b33e5b0
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+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+// Seed corpus for FuzzAssembleRISCV64: the Zbb/Zba/Zbs/Zicond bit-manipulation
+// and address-generation set, with every unary form's W variant and the
+// shamt-range immediate forms.
+
+#include "textflag.h"
+
+TEXT ·unary(SB), NOSPLIT, $0
+	CLZ   X5, X6
+	CLZW  X5, X6
+	CTZ   X5, X6
+	CTZW  X5, X6
+	CPOP  X5, X6
+	CPOPW X5, X6
+	SEXTB X5, X6
+	SEXTH X5, X6
+	ZEXTH X5, X6
+	ORCB  X5, X6
+	REV8  X5, X6
+	RET
+
+TEXT ·rolRor(SB), NOSPLIT, $0
+	ROL    X7, X5, X6
+	ROR    X7, X5, X6
+	RORI   $0, X5, X6
+	RORI   $63, X5, X6
+	ANDN   X7, X5, X6
+	ORN    X7, X5, X6
+	XNOR   X7, X5, X6
+	MAX    X7, X5, X6
+	MAXU   X7, X5, X6
+	MIN    X7, X5, X6
+	MINU   X7, X5, X6
+	CLMUL  X7, X5, X6
+	CLMULH X7, X5, X6
+	CLMULR X7, X5, X6
+	RET
+
+TEXT ·addrGen(SB), NOSPLIT, $0
+	SH1ADD   X7, X5, X6
+	SH2ADD   X7, X5, X6
+	SH3ADD   X7, X5, X6
+	SH1ADDUW X7, X5, X6
+	SH2ADDUW X7, X5, X6
+	SH3ADDUW X7, X5, X6
+	ADDUW    X7, X5, X6
+	RET
+
+TEXT ·bitImm(SB), NOSPLIT, $0
+	BCLR  $31, X5, X6
+	BEXT  $63, X5, X6
+	BINV  $0, X5, X6
+	BSET  $31, X5, X6
+	BCLRI $63, X5, X6
+	BEXTI $31, X5, X6
+	BINVI $63, X5, X6
+	BSETI $63, X5, X6
+	RET
+
+TEXT ·condZero(SB), NOSPLIT, $0
+	CZEROEQZ X7, X5, X6
+	CZERONEZ X7, X5, X6
+	RET