feat(asm): encode the riscv64 quad-precision family and fix the fp cvt paths

Assisted-by: GLM 5.3 Flash
2026-10-07 00:47:27 +02:00
1 parent 955bc6643e
commit 9b751f6e58
@@ -0,0 +1,86 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+package asm
+
+import "testing"
+
+// TestRISCVQuadFP_golden pins the quad-precision ("Q") family on golden
+// vectors from the specification.  The Go toolchain's object table carries
+// the encodings but its assembler accepts no Q mnemonic, so no oracle run
+// is possible: the words below follow the Q extension's encoding table with
+// the Plan 9 operand order the other widths use (first operand in rs2, the
+// bare float-to-integer conversions carrying the RTZ rounding mode).
+func TestRISCVQuadFP_golden(t *testing.T) {
+	fn := firstTextRISCV(t, `#include "textflag.h"
+TEXT ·q(SB), NOSPLIT, $0
+	FLQ		8(X5), F3
+	FSQ		F3, 8(X5)
+	FADDQ	F1, F2, F3
+	FSUBQ	F1, F2, F3
+	FMULQ	F1, F2, F3
+	FDIVQ	F1, F2, F3
+	FSQRTQ	F2, F1
+	FMINQ	F1, F2, F3
+	FMAXQ	F1, F2, F3
+	FEQQ	F3, F2, X5
+	FLTQ	F3, F2, X5
+	FLEQ	F3, F2, X5
+	FSGNJQ	F1, F2, F3
+	FSGNJNQ	F1, F2, F3
+	FSGNJXQ	F1, F2, F3
+	FMADDQ	F1, F2, F3, F4
+	FMSUBQ	F1, F2, F3, F4
+	FNMSUBQ	F1, F2, F3, F4
+	FNMADDQ	F1, F2, F3, F4
+	FCVTSQ	F5, F2
+	FCVTDQ	F5, F2
+	FCVTQS	F2, F5
+	FCVTQD	F2, F5
+	FCVTWQ	F2, X5
+	FCVTWUQ	F2, X5
+	FCVTLQ	F2, X5
+	FCVTLUQ	F2, X5
+	FCVTQW	X5, F2
+	FCVTQWU	X5, F2
+	FCVTQL	X5, F2
+	FCVTQLU	X5, F2
+	FCLASSQ	F2, X5
+	RET
+`)
+	code := assembleRISCVHelper(t, fn)
+	riscvWants(t, code,
+		0x0082C187, // flq f3, 8(x5)
+		0x0032C427, // fsq f3, 8(x5)
+		0x061101D3, // fadd.q f3, f2, f1
+		0x0E1101D3, // fsub.q
+		0x161101D3, // fmul.q
+		0x1E1101D3, // fdiv.q
+		0x5E0100D3, // fsqrt.q f1, f2
+		0x2E1101D3, // fmin.q f3, f2, f1
+		0x2E1111D3, // fmax.q
+		0xA63122D3, // feq.q x5, f2, f3
+		0xA63112D3, // flt.q
+		0xA63102D3, // fle.q
+		0x261101D3, // fsgnj.q
+		0x261111D3, // fsgnjn.q
+		0x261121D3, // fsgnjx.q
+		0x1E208243, // fmadd.q f4, f1, f2, f3
+		0x1E208247, // fmsub.q
+		0x1E20824B, // fnmsub.q
+		0x1E20824F, // fnmadd.q
+		0x40328153, // fcvt.s.q f2, f5
+		0x42328153, // fcvt.d.q f2, f5
+		0x460102D3, // fcvt.q.s f5, f2
+		0x461102D3, // fcvt.q.d f5, f2
+		0xC60112D3, // fcvt.w.q x5, f2
+		0xC61112D3, // fcvt.wu.q
+		0xC62112D3, // fcvt.l.q
+		0xC63112D3, // fcvt.lu.q
+		0xD6028153, // fcvt.q.w f2, x5
+		0xD6128153, // fcvt.q.wu
+		0xD6228153, // fcvt.q.l
+		0xD6328153, // fcvt.q.lu
+		0xE60112D3, // fclass.q x5, f2
+	)
+}