feat(asm): encode the riscv64 quad-precision family and fix the fp cvt paths
Assisted-by: GLM 5.3 Flash
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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import (
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"os"
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"path/filepath"
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"testing"
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)
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// TestRISCVScalarFP_Differential proves the scalar single- and
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// double-precision families against the toolchain: sections 21.6 through
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// 22.7 of the "F" and "D" specifications' computational, conversion, move,
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// sign-injection, compare and classify instructions in the toolchain's own
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// testdata wording, assembled by gasm and by go tool asm must agree word
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// for word.
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func TestRISCVScalarFP_Differential(t *testing.T) {
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src := `#include "textflag.h"
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TEXT ·fp(SB), NOSPLIT, $0
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// 21.6: Single-Precision Floating-Point Computational Instructions
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FADDS F1, F0, F2 // 53011000
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FSUBS F1, F0, F2 // 53011008
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FMULS F1, F0, F2 // 53011010
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FDIVS F1, F0, F2 // 53011018
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FMINS F1, F0, F2 // 53011028
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FMAXS F1, F0, F2 // 53111028
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FSQRTS F0, F1 // d3000058
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// 21.7: Single-Precision Floating-Point Conversion and Move Instructions
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FCVTWS F0, X5 // d31200c0
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FCVTWS.RNE F0, X5 // d30200c0
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FCVTWS.RTZ F0, X5 // d31200c0
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FCVTWS.RDN F0, X5 // d32200c0
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FCVTWS.RUP F0, X5 // d33200c0
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FCVTWS.RMM F0, X5 // d34200c0
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FCVTLS F0, X5 // d31220c0
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FCVTLS.RNE F0, X5 // d30220c0
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FCVTLS.RTZ F0, X5 // d31220c0
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FCVTLS.RDN F0, X5 // d32220c0
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FCVTLS.RUP F0, X5 // d33220c0
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FCVTLS.RMM F0, X5 // d34220c0
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FCVTSW X5, F0 // 538002d0
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FCVTSL X5, F0 // 538022d0
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FCVTWUS F0, X5 // d31210c0
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FCVTWUS.RNE F0, X5 // d30210c0
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FCVTWUS.RTZ F0, X5 // d31210c0
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FCVTWUS.RDN F0, X5 // d32210c0
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FCVTWUS.RUP F0, X5 // d33210c0
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FCVTWUS.RMM F0, X5 // d34210c0
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FCVTLUS F0, X5 // d31230c0
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FCVTLUS.RNE F0, X5 // d30230c0
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FCVTLUS.RTZ F0, X5 // d31230c0
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FCVTLUS.RDN F0, X5 // d32230c0
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FCVTLUS.RUP F0, X5 // d33230c0
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FCVTLUS.RMM F0, X5 // d34230c0
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FCVTSWU X5, F0 // 538012d0
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FCVTSLU X5, F0 // 538032d0
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FSGNJS F1, F0, F2 // 53011020
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FSGNJNS F1, F0, F2 // 53111020
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FSGNJXS F1, F0, F2 // 53211020
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FMVXS F0, X5 // d30200e0
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FMVSX X5, F0 // 538002f0
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FMVXW F0, X5 // d30200e0
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FMVWX X5, F0 // 538002f0
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FMADDS F1, F2, F3, F4 // 43822018
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FMSUBS F1, F2, F3, F4 // 47822018
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FNMSUBS F1, F2, F3, F4 // 4b822018
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FNMADDS F1, F2, F3, F4 // 4f822018
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// 21.8: Single-Precision Floating-Point Compare Instructions
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FEQS F0, F1, X7 // d3a300a0
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FLTS F0, F1, X7 // d39300a0
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FLES F0, F1, X7 // d38300a0
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// 21.9: Single-Precision Floating-Point Classify Instruction
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FCLASSS F0, X5 // d31200e0
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// 22.3: Double-Precision Load and Store Instructions
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FLD (X5), F0 // 07b00200
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FLD 4(X5), F0 // 07b04200
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FSD F0, (X5) // 27b00200
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FSD F0, 4(X5) // 27b20200
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// 22.4: Double-Precision Floating-Point Computational Instructions
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FADDD F1, F0, F2 // 53011002
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FSUBD F1, F0, F2 // 5301100a
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FMULD F1, F0, F2 // 53011012
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FDIVD F1, F0, F2 // 5301101a
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FMIND F1, F0, F2 // 5301102a
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FMAXD F1, F0, F2 // 5311102a
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FSQRTD F0, F1 // d300005a
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// 22.5: Double-Precision Floating-Point Conversion and Move Instructions
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FCVTWD F0, X5 // d31200c2
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FCVTWD.RNE F0, X5 // d30200c2
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FCVTWD.RTZ F0, X5 // d31200c2
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FCVTWD.RDN F0, X5 // d32200c2
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FCVTWD.RUP F0, X5 // d33200c2
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FCVTWD.RMM F0, X5 // d34200c2
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FCVTLD F0, X5 // d31220c2
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FCVTLD.RNE F0, X5 // d30220c2
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FCVTLD.RTZ F0, X5 // d31220c2
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FCVTLD.RDN F0, X5 // d32220c2
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FCVTLD.RUP F0, X5 // d33220c2
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FCVTLD.RMM F0, X5 // d34220c2
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FCVTDW X5, F0 // 538002d2
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FCVTDL X5, F0 // 538022d2
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FCVTWUD F0, X5 // d31210c2
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FCVTWUD.RNE F0, X5 // d30210c2
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FCVTWUD.RTZ F0, X5 // d31210c2
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FCVTWUD.RDN F0, X5 // d32210c2
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FCVTWUD.RUP F0, X5 // d33210c2
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FCVTWUD.RMM F0, X5 // d34210c2
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FCVTLUD F0, X5 // d31230c2
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FCVTLUD.RNE F0, X5 // d30230c2
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FCVTLUD.RTZ F0, X5 // d31230c2
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FCVTLUD.RDN F0, X5 // d32230c2
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FCVTLUD.RUP F0, X5 // d33230c2
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FCVTLUD.RMM F0, X5 // d34230c2
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FCVTDWU X5, F0 // 538012d2
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FCVTDLU X5, F0 // 538032d2
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FCVTSD F0, F1 // d3001040
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FCVTDS F0, F1 // d3000042
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FSGNJD F1, F0, F2 // 53011022
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FSGNJND F1, F0, F2 // 53111022
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FSGNJXD F1, F0, F2 // 53211022
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FMVXD F0, X5 // d30200e2
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FMVDX X5, F0 // 538002f2
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FMADDD F1, F2, F3, F4 // 4382201a
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FMSUBD F1, F2, F3, F4 // 4782201a
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FNMSUBD F1, F2, F3, F4 // 4b82201a
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FNMADDD F1, F2, F3, F4 // 4f82201a
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// 22.6: Double-Precision Floating-Point Compare Instructions
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FEQD F0, F1, X7 // d3a300a2
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FLTD F0, F1, X7 // d39300a2
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FLED F0, F1, X7 // d38300a2
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// 22.7: Double-Precision Floating-Point Classify Instruction
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FCLASSD F0, X5 // d31200e2
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RET
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`
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dir := t.TempDir()
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path := filepath.Join(dir, "fp_riscv64.s")
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if err := os.WriteFile(path, []byte(src), 0o644); err != nil {
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t.Fatal(err)
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}
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assertRISCVDifferential(t, path, src, "fp")
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}
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