feat(riscv64,loong64): PCALIGN, branch relaxation and operand shapes

Assisted-by: GLM 5.3 Flash

asm/riscv_encode.go

@@ -219,6 +219,9 @@ var riscvInstrTable = map[string]riscvEnc{
 	"DIVUW": {0x3B, 0x5, 0x01},
 	"REMW":  {0x3B, 0x6, 0x01},
 	"REMUW": {0x3B, 0x7, 0x01},
+	// Zicond conditional zeroing.
+	"CZEROEQZ": {0x33, 0x5, 0x07},
+	"CZERONEZ": {0x33, 0x7, 0x07},
 	// RV64I, I-type arithmetic.
 	"ADDI":  {0x13, 0x0, 0x00},
 	"ADDIW": {0x1B, 0x0, 0x00},
@@ -247,13 +250,21 @@ var riscvInstrTable = map[string]riscvEnc{
 	"BGE":  {0x63, 0x5, 0x00},
 	"BLTU": {0x63, 0x6, 0x00},
 	"BGEU": {0x63, 0x7, 0x00},
+	// The swapped-spelling comparison forms: encoded as BLT/BGE/BLTU/BGEU
+	// with the register operands swapped.
+	"BGT":  {0x63, 0x4, 0x00},
+	"BLE":  {0x63, 0x5, 0x00},
+	"BGTU": {0x63, 0x6, 0x00},
+	"BLEU": {0x63, 0x7, 0x00},
 	// U-type.
 	"LUI":   {0x37, 0x0, 0x00},
 	"AUIPC": {0x17, 0x0, 0x00},
 	// System.
-	"ECALL":  {0x73, 0x0, 0x00},
-	"EBREAK": {0x73, 0x0, 0x00},
-	"FENCE":  {0x0F, 0x0, 0x00},
+	"ECALL":     {0x73, 0x0, 0x00},
+	"EBREAK":    {0x73, 0x0, 0x00},
+	"FENCE":     {0x0F, 0x0, 0x00},
+	"FENCE.TSO": {0x0F, 0x0, 0x00},
+	"PAUSE":     {0x0F, 0x0, 0x00},
 	// JALR, indirect jump/call (I-type).
 	"JALR": {0x67, 0x0, 0x00},
 
@@ -303,7 +314,14 @@ var riscvInstrTable = map[string]riscvEnc{
 	"FMIND": {0x53, 0x0, 0x15},
 	"FMAXD": {0x53, 0x1, 0x15},
 	// FP sign injection (double): rs2 carries the sign source.
-	"FSGNJD": {0x53, 0x0, 0x11},
+	"FSGNJD":  {0x53, 0x0, 0x11},
+	"FSGNJS":  {0x53, 0x0, 0x10},
+	"FSGNJX":  {0x53, 0x0, 0x14},
+	"FSGNJXD": {0x53, 0x0, 0x15},
+	"FSGNJXS": {0x53, 0x0, 0x14},
+	"FSGNJND": {0x53, 0x1, 0x11},
+	"FSGNJNS": {0x53, 0x1, 0x10},
+	"FSGNJNX": {0x53, 0x1, 0x14},
 
 	// RV64A, load-reserved / store-conditional (funct5 0x02 / 0x03).
 	// The toolchain gives LR acquire ordering (aq = 1) and SC release
@@ -375,6 +393,10 @@ var riscvCvtTable = map[string]riscvCvtEnc{
 	"FMVDX": {0x79, 0x0, 0x53}, // int64 → float64 (bit move)
 	"FMVXW": {0x70, 0x0, 0x53}, // float32 → int32 (bit move)
 	"FMVWX": {0x78, 0x0, 0x53}, // int32 → float32 (bit move)
+	// The toolchain's W/D suffix spellings of the same moves.
+	"FMVXS": {0x70, 0x0, 0x53},
+	"FMVFS": {0x78, 0x0, 0x53},
+	"FMVSX": {0x79, 0x0, 0x53},
 }
 
 // riscvCvtType encodes an FP conversion instruction.