chore: prepare release v0.36.0

Assisted-by: GLM 5.3 Flash

docs/asm/LOONG64.md

@@ -41,6 +41,12 @@ R13` is `add.d R13, R12, R11`, and the two-operand form
 - Jump and branch instructions keep the GNU order: `BEQ R0, R4, label1`.
 - The bitfield family is `BSTRINSW`, `BSTRINSV`, `BSTRPICKW`, `BSTRPICKV`
   `$<msb>, <Rj>, $<lsb>, <Rd>`.
+- **The register-pair spelling** `R4:R5` names two registers in one
+  operand, the way the toolchain's pair syntax does: the colon splits the
+  operand and the halves swap, so `MULV R4:R5, R6` encodes exactly as
+  `MULV R5, R4, R6`. Any instruction shape accepts the spelling, decided
+  afterwards by ordinary operand matching, and a malformed pair fails with
+  the toolchain's wording.
 
 ## Addressing