chore: prepare release v0.36.0

Assisted-by: GLM 5.3 Flash

docs/asm/RISCV64.md

@@ -55,6 +55,10 @@ the FCSR.
   a literal pool in the binary.
 - A 32-bit constant is accepted by `ADDI`, `ANDI`, `ORI` and `XORI`, and
   the assembler synthesises values that exceed the 12-bit encoding window.
+- A memory offset beyond the 12-bit immediate expands the way the
+  toolchain's loads and stores do: the upper bits go into the assembler's
+  temporary register and the access runs against it, byte-identically, and
+  an offset the toolchain refuses is refused with its wording.
 - `MOVF` and `MOVD` materialise floating-point constants, encoding them as
   `FLW` and `FLD` from a pool location unless the constant is exactly 0.0.
 
@@ -85,6 +89,15 @@ of the source, and register choice influences how much compresses.
 Hand-writing compressed instructions in source is accepted but discouraged.
 The debug flag `compressinstructions=0` turns the automatic conversion off.
 
+## Pseudo-operations
+
+- `END` is accepted anywhere and emits nothing, the function-end marker
+  the toolchain's front end also swallows.
+- `GETCALLERPC` reads the return address the frame state describes: a leaf
+  function reads `X1`, a framed body reads the prologue's save slot at
+  `0(SP)`, and both spellings take the compressed encoding where the
+  register choice allows it.
+
 ## Vector extension
 
 `VSETVLI` writes its vtype components in uppercase with the destination