feat(disasm): render the loong64 families x/arch names Unknown

x/arch's Plan 9 renderer decodes thirty-odd scalar loong64 operations
perfectly but prints them as "Unknown OP args", and names the
sign-extension pair EXT.W.B/EXT.W.H "?".  The supplementary naming
pass re-renders them with the toolchain's own spellings: the families
whose operand order x/arch already prints the Plan 9 way trade only
the mnemonic, and the pointer loads and stores, the acquire loads,
the release stores, PRELD and ALSL are rebuilt from the decoded
arguments with the toolchain's operand order and its raw displacement
reading.  ADDU16I.D, a macro helper the assembler never takes as
input, keeps the decoder's Unknown render.

The loong64 parity fixture grows from 73 to 385 rows, pinning every
unique four-byte corpus word the decoder accepts, and the LL/SC
displacement divergence in the encoder is documented for asm.

Assisted-by: GLM 5.3

disasm/parity_test.go

@@ -208,9 +208,11 @@ var toolchainRenderNames = map[string]bool{
 // where the pinned bytes took the alternative).  arm64: the CRC32 forms
 // take the wrong Rm; the register-indexed load and store forms lose the
 // index operand; BFXIL encodes as BFI with shifted immediates.  loong64:
-// the SC displacement encodes unscaled.  riscv64: FSGNJXS encodes as
-// FMIN.S; FCLASSS and FCLASSD encode as MOVF; the AUIPC immediate loses
-// its high bits.  Keyed by the fixture text.
+// the LL and SC displacements encode scaled where the toolchain takes them
+// raw ("LL 1024(R5), R4" assembles to a field of 256, and the re-decoded
+// text reads 256(R5)).  riscv64: FSGNJXS encodes as FMIN.S; FCLASSS and
+// FCLASSD encode as MOVF; the AUIPC immediate loses its high bits.  Keyed
+// by the fixture text.
 var encoderDivergences = map[string]bool{
 	"CMOVLE 0(BX), DX":             true,
 	"MOVQ FS:0, DX":                true,
@@ -225,6 +227,9 @@ var encoderDivergences = map[string]bool{
 	"MOVD R27, (R5)(R15.UXTW<<3)":  true,
 	"MOVH R11, (R27)(R14.SXTW<<1)": true,
 	"SC R4, 1024(R5)":              true,
+	"LL 1024(R5), R4":              true,
+	"LLV 1024(R5), R4":             true,
+	"SCV R4, 1024(R5)":             true,
 	"FSGNJXS F1, F0, F2":           true,
 	"FCLASSS F0, X5":               true,
 	"FCLASSD F0, X5":               true,