fix(asm): reject the operand-starved riscv64 spellings instead of panicking

Assisted-by: GLM 5.3

asm/riscv_assemble.go

@@ -570,6 +570,11 @@ func riscvRevShiftSize(mnem string, ops []*ast.Operand) int {
 	if mnem != "ROR" && mnem != "RORI" {
 		return 4 // SLLIW has no compressed form
 	}
+	if len(ops) < 2 {
+		// A malformed one-operand form: encoding rejects it with a
+		// diagnostic, and the layout pass only needs a word count.
+		return 4
+	}
 	imm := int(immFromOperand(ops[0]))
 	rs1 := regFromOperand(ops[1])
 	rd := rs1
@@ -4830,6 +4835,9 @@ func encodeRISCVVecLS(mnem string, ops []*ast.Operand) ([]byte, bool, error) {
 	if !ok {
 		return nil, true, fmt.Errorf("unsupported vector load/store %q", mnem)
 	}
+	if len(ops) < 2 {
+		return nil, true, fmt.Errorf("%s expects at least 2 operands, got %d", mnem, len(ops))
+	}
 	op := uint32(0x27)
 	if v.load {
 		op = 0x07