fix(asm): reject the operand-starved riscv64 spellings instead of panicking

Assisted-by: GLM 5.3

asm/riscv_frame.go

@@ -96,8 +96,10 @@ func riscvIsLeaf(t *ast.Text) bool {
 		case "JALR":
 			// JALR rd, offset(rs1) links when the destination register (the
 			// first operand) is X1; JALR rs1, rd links when the second
-			// register is X1; JALR offset(rs1) always links to X1.
-			if len(in.Operands) == 1 {
+			// register is X1; JALR offset(rs1) always links to X1.  A bare
+			// operand-less spelling is malformed and encoding rejects it;
+			// conservatively count it as a link so the frame stays honest.
+			if len(in.Operands) <= 1 {
 				return false
 			}
 			if isMemOperand(in.Operands[1]) {