fix(asm): correct RISC-V frame layout and RVC encodings

Assisted-by: GLM 5.2

CHANGELOG.md

@@ -32,11 +32,20 @@ Unreleased changes on the `development` branch.
   relocation (the layout `cmd/asm` writes, not the ELF HI20/LO12 pair), so the
   object links into a cross-compiled `go build` for `GOARCH=riscv64`.  An
   end-to-end link test substitutes the gasm object and reads the symbol back
-  with `go tool nm`; the rewrite also corrects the relocation `after` field
-  and the compressed `RET` encoding (C.JR ra).
+  with `go tool nm`; the rewrite also corrects the relocation `after` field.
 
 ### Fixed
 
+- **RISC-V frame model and RVC encodings.**  The riscv64 frame layout now
+  matches `go tool asm`: the prologue/epilogue save and restore the link
+  register (LR) instead of S0, with the correct autosize (locals + 8) and the
+  RVC-compressed prologue/epilogue instructions; `RET` emits the uncompressed
+  `JALR X0, 0(X1)` the toolchain writes; the `C.ADDI`/`C.LI`/`C.LUI`/`C.ADDIW`
+  opcode bit and the `C.ADD` CR-type encoding are fixed; and the `LR`/`TMP`
+  register aliases now resolve to X1 and X31.  The pcsp/pcfile/pcline tables
+  are populated from the recorded stack-adjustment and source-line data, and
+  a byte-exact ground-truth test compares framed and leaf functions against
+  `GOARCH=riscv64 go tool asm`.
 - **Debugger watchpoint slots.**  `gasm debug`'s `watch` command always used
   hardware watchpoint slot 0, so a second `watch` call silently overwrote
   the first.  Watchpoint slots are now tracked in the `Session` (DR0–DR3);