fix(asm): correct RISC-V frame layout and RVC encodings

Assisted-by: GLM 5.2

asm/riscv_encode.go

@@ -13,7 +13,7 @@ func riscvRegNum(name string) int {
 	// Numbered integer registers.
 	case "X0", "ZERO":
 		return 0
-	case "X1", "RA":
+	case "X1", "RA", "LR":
 		return 1
 	case "X2", "SP":
 		return 2
@@ -21,9 +21,9 @@ func riscvRegNum(name string) int {
 		return 3
 	case "X4", "TP":
 		return 4
-	case "X5", "T0", "LR":
+	case "X5", "T0":
 		return 5
-	case "X6", "T1", "TMP":
+	case "X6", "T1":
 		return 6
 	case "X7", "T2":
 		return 7
@@ -73,7 +73,7 @@ func riscvRegNum(name string) int {
 		return 29
 	case "X30", "T5":
 		return 30
-	case "X31", "T6":
+	case "X31", "T6", "TMP":
 		return 31
 	// Floating-point registers (F0-F31).
 	case "F0", "FT0":
@@ -457,7 +457,7 @@ func rvcCR(funct4, rd, rs2 uint32) uint16 {
 // rvcCI encodes a CI-type (immediate) compressed instruction.
 // Used for C.ADDI, C.LI, C.LUI, C.ADDIW — linear 6-bit immediate.
 func rvcCI(funct3, rd uint32, imm uint32) uint16 {
-	return uint16((funct3 << 13) | ((imm>>5)&1)<<12 | (rd << 7) | (imm&0x1F)<<2 | 0x2)
+	return uint16((funct3 << 13) | ((imm>>5)&1)<<12 | (rd << 7) | (imm&0x1F)<<2 | 0x1)
 }
 
 // rvcLSP encodes a CI-type stack-relative load: C.LDSP (funct3=3) or