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fix(asm): correct RISC-V frame layout and RVC encodings

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Assisted-by: GLM 5.2
This commit is contained in:
petrbalvin
2026-08-13 14:41:57 +02:00
parent 9b5c878f9e
commit b78b6c5004
11 changed files with 489 additions and 249 deletions
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asm/riscv_goobj_test.go
+5 -4
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@@ -40,8 +40,8 @@ DATA answer<>+0(SB)/8, $42
t.Fatalf("AssembleFileRISCV: %v", err)
}
fn := img.Funcs[0]
if fn.Size != 26 {
t.Fatalf("function size = %d, want 26", fn.Size)
if fn.Size != 28 {
t.Fatalf("function size = %d, want 28", fn.Size)
}
if len(fn.Relocs) != 3 {
t.Fatalf("relocs = %d, want 3", len(fn.Relocs))
@@ -95,14 +95,15 @@ DATA answer<>+0(SB)/8, $42
}
// The function code: three AUIPC+second-instruction pairs with zero
// immediates, then the compressed return.
// immediates, then the uncompressed JALR X0, 0(X1) the toolchain emits
// for RET.
code := img.Code[fn.Offset : fn.Offset+fn.Size]
want := append(wordLE(riscvUType(riscvEnc{0x17, 0x0, 0x00}, 10, 0)), wordLE(riscvIType(riscvEnc{0x13, 0x0, 0x00}, 10, 10, 0))...)
want = append(want, wordLE(riscvUType(riscvEnc{0x17, 0x0, 0x00}, 11, 0))...)
want = append(want, wordLE(riscvIType(riscvEnc{0x03, 0x3, 0x00}, 11, 11, 0))...)
want = append(want, wordLE(riscvUType(riscvEnc{0x17, 0x0, 0x00}, 31, 0))...)
want = append(want, wordLE(riscvSType(riscvEnc{0x23, 0x3, 0x00}, 31, 12, 0))...)
want = append(want, 0x82, 0x80) // C.JR ra
want = append(want, 0x67, 0x80, 0x00, 0x00) // JALR X0, 0(X1)
if !bytes.Equal(code, want) {
t.Errorf("code = % x\nwant % x", code, want)
}