feat(asm): encode the amd64 and loong64 tails of the corpus testdata
Assisted-by: GLM 5.3
This commit is contained in:
+30
-1
@@ -17,13 +17,28 @@ import "strings"
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// size. The high flag marks the legacy high-byte registers AH/CH/DH/BH, which
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// occupy indices 4-7 yet take no REX prefix, unlike SPL/BPL/SIL/DIL that share
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// those indices but require one. The mask flag marks the AVX-512 opmask
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// registers K0-K7, the fp flag the x87 stack registers F0-F7.
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// registers K0-K7, the fp flag the x87 stack registers F0-F7, the mmx flag the
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// MMX registers M0-M7, the seg field a bare segment register (FS, GS) and the
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// ctl field the control and debug registers, whose number rides an
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// instruction's reg field rather than r/m.
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type Reg struct {
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idx int
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size int // informational width implied by the name; the mnemonic decides
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high bool // AH/CH/DH/BH
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mask bool // K0-K7 opmask register
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fp bool // F0-F7 x87 stack register
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mmx bool // M0-M7 MMX register
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seg int // segment register number plus one (ES=1..GS=6); 0 = not one
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ctl byte // 0 none, 1 CRn control register, 2 DRn debug register
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}
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// segNumber returns the segment register number (ES=0..GS=5) when r names a
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// bare segment register.
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func (r Reg) segNumber() (int, bool) {
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if r.seg == 0 {
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return 0, false
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}
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return r.seg - 1, true
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}
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// Index returns the register number (0-15 for GPRs, 0-31 for vectors).
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@@ -149,6 +164,20 @@ func buildRegByName() map[string]Reg {
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for i := 0; i <= 7; i++ {
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m["F"+itoa(i)] = Reg{idx: i, size: 8, fp: true}
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}
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// MMX: M0..M7.
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for i := 0; i <= 7; i++ {
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m["M"+itoa(i)] = Reg{idx: i, size: 8, mmx: true}
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}
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// Bare segment registers: ES, CS, SS, DS, FS, GS (the memory-base and
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// index spellings of FS and GS are handled before register lookup).
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for i, n := range []string{"ES", "CS", "SS", "DS", "FS", "GS"} {
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m[n] = Reg{idx: i, size: 2, seg: i + 1}
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}
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// Control and debug registers: CR0..CR15, DR0..DR15.
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for i := 0; i <= 15; i++ {
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m["CR"+itoa(i)] = Reg{idx: i, size: 8, ctl: 1}
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m["DR"+itoa(i)] = Reg{idx: i, size: 8, ctl: 2}
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}
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return m
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}
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