feat(arch): the SVE2.1 last-active vector and compare families

Assisted-by: GLM 5.3 Flash

asm/arm64_ext_asm_test.go

@@ -876,7 +876,7 @@ func TestArm64AssembleExtensionStage4Refusals(t *testing.T) {
 		{"ZADDHNB Z22.D, Z10.D, Z8.H", "want .S"},
 		{"ZADDHNB Z22.Q, Z10.Q, Z8.D", "want .H, .S or .D"},
 		{"ZADDHNB Z22.S, Z10.S, Z8", "carries no arrangement suffix"},
-		{"ZADDP Z15.B, Z0.B, P3.Z, Z0.B", "merging qualifier"},
+		{"ZADDP Z15.B, Z0.B, P3.Z, Z0.B", "/M qualifier"},
 		{"ZADDPT Z7.S, Z6.S, Z23.S", "want .D"},
 		{"ZADDQV Z25.S, P9, V5.S4", "outside P0-P7"},
 		{"ZADDQV Z25.S, P3/M, V5.S4", "takes no qualifier"},