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feat(arch): add the write mask to the packed amd64 destinations

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Assisted-by: GLM 5.3 Flash
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petrbalvin committed 2026-10-07 02:21:57 +02:00
1 parent 631fb8a8d7
commit c2adde948f
3 files changed
+225 -42
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arch/amd64_ext_test.go
+58
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@@ -523,6 +523,34 @@ var amd64GoldenRows = []amd64GoldenRow{
{"vcvtne2ps2bf16 high registers", "VCVTNE2PS2BF16",
[]ExtOperand{ExtZmm(21), ExtZmm(20), ExtZmm(23)},
"62a2574072fc", ""},
// The write mask, the SDM's {k1}{z} decorations on the packed
// destinations: EVEX.aaa carries the masking register, EVEX.z the
// zeroing bit, laid over the words the unmasked rows above prove byte
// for byte (the x86-64-avx512_fp16.d and avx512_bf16.d listings carry
// the same {k7}{z} rows). Zeroing keeps the destination's inactive
// lanes no longer: they become zeros.
{"vaddph k7 zeroing", "VADDPH",
[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtWriteMasked(ExtZmm(30), 7, true)},
"620514c758f4", ""},
{"vaddph k1 merging", "VADDPH",
[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtWriteMasked(ExtZmm(30), 1, false)},
"6205144158f4", ""},
{"vaddph k7 zeroing, memory source", "VADDPH",
[]ExtOperand{ExtZmm(28), ExtMemory(9, 0), ExtWriteMasked(ExtZmm(30), 7, true)},
"62451cc75831", ""},
{"vcvtne2ps2bf16 k7 zeroing", "VCVTNE2PS2BF16",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtWriteMasked(ExtZmm(6), 7, true)},
"62f257cf72f4", ""},
{"vdpbf16ps k5 merging", "VDPBF16PS",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtWriteMasked(ExtZmm(6), 5, false)},
"62f2564d52f4", ""},
{"vcvtneps2bf16 k6 merging", "VCVTNEPS2BF16",
[]ExtOperand{ExtYmm(5), ExtWriteMasked(ExtXmm(6), 6, false)},
"62f27e2e72f5", ""},
{"vsqrtph k3 zeroing", "VSQRTPH",
[]ExtOperand{ExtZmm(29), ExtWriteMasked(ExtZmm(30), 3, true)},
"62057ccb51f5", ""},
}
// amd64ResolveEntry finds the table entry a golden row exercises: the entry
@@ -778,6 +806,30 @@ func TestAmd64ExtRejects(t *testing.T) {
{"a scale the multipliers do not carry", "VADDPH",
[]ExtOperand{ExtZmm(29), ExtScaledMemory(1, 14, 3, 0), ExtZmm(30)},
"outside the byte multipliers"},
{"K0 as the write mask", "VADDPH",
[]ExtOperand{ExtZmm(28), ExtZmm(30), ExtWriteMasked(ExtZmm(29), 0, true)},
"outside the masking registers k1-k7"},
{"zeroing without a write mask", "VADDPH",
[]ExtOperand{ExtZmm(28), ExtZmm(30), ExtOperand{Kind: ExtZMM, Reg: 29, Zeroing: true}},
"carries zeroing without a write mask"},
{"write mask on the scalar arithmetic", "VADDSH",
[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtWriteMasked(ExtXmm(30), 3, true)},
"the entry's destination takes none"},
{"write mask on the compare without a vector destination", "VCOMISH",
[]ExtOperand{ExtXmm(29), ExtWriteMasked(ExtXmm(30), 2, false)},
"the entry's destination takes none"},
{"write mask on the intersection's vector source", "VP2INTERSECTD",
[]ExtOperand{ExtWriteMasked(ExtZmm(2), 3, false), ExtZmm(1), ExtMask(0)},
"the position takes none"},
{"write mask on a source position", "VADDPH",
[]ExtOperand{ExtZmm(29), ExtWriteMasked(ExtZmm(28), 3, false), ExtZmm(30)},
"the position takes none"},
{"write mask on the control form's destination", "VGETMANTSH",
[]ExtOperand{ExtImmediate(0x0b), ExtXmm(29), ExtXmm(28), ExtWriteMasked(ExtXmm(30), 7, true)},
"the position takes none"},
{"write mask where the destination is memory", "VCOMISH",
[]ExtOperand{ExtXmm(30), ExtOperand{Kind: ExtMem, Reg: 9, HasMask: true, Mask: 2}},
"the entry's destination takes none"},
} {
in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
_, err := in.Encode(tt.ops)
@@ -835,6 +887,12 @@ func TestAmd64ExtMemoryFormRejects(t *testing.T) {
{"broadcast destination on the store", "VMOVSH", store,
[]ExtOperand{ExtXmm(30), ExtBroadcast(9, 0)},
"carries a broadcast, the entry's memory operand takes none"},
{"write mask on the store's memory destination", "VMOVSH", store,
[]ExtOperand{ExtXmm(30), ExtOperand{Kind: ExtMem, Reg: 9, HasMask: true, Mask: 2}},
"the memory operand takes none"},
{"zeroing on the store's memory destination", "VMOVSH", store,
[]ExtOperand{ExtXmm(30), ExtOperand{Kind: ExtMem, Reg: 9, Zeroing: true}},
"the memory operand takes none"},
} {
in := amd64ExtInstr(t, tt.mnem, ExtXMM, tt.pick)
_, err := in.Encode(tt.ops)