feat(arch): add the write mask to the packed amd64 destinations

Assisted-by: GLM 5.3 Flash

arch/arm64_ext.go

@@ -183,6 +183,17 @@ type ExtOperand struct {
 	Index    int
 	Scale    int
 	HasIndex bool
+	// Mask spells the write mask of an amd64 EVEX destination, the {k1}
+	// through {k7} decorations: only the masked lanes take the result.
+	// HasMask separates a spelled mask from the unmasked destination, and
+	// K0 never masks, so the register runs 1..7.  Only the packed
+	// destinations of the entries that carry Mask accept it.
+	Mask    int
+	HasMask bool
+	// Zeroing spells the {z} decoration beside a write mask: the inactive
+	// lanes become zero instead of keeping the destination.  It is valid
+	// only together with a spelled mask.
+	Zeroing bool
 }
 
 // ExtVector builds a scalable vector operand, ADD Z1.S style.
@@ -503,6 +514,13 @@ type ExtInstr struct {
 	// forms and the full-width sources do not.  The arm64 entries all
 	// carry the zero value.
 	Bcast bool
+	// Mask records that the entry's packed destination takes the write
+	// mask, the SDM's {k1}{z} decorations: EVEX.aaa carries the masking
+	// register and EVEX.z the zeroing bit.  The packed forms carry it; the
+	// scalar forms, the compares without a vector destination, the
+	// opmask-destination forms and the load and store shapes do not.  The
+	// arm64 entries all carry the zero value.
+	Mask bool
 }
 
 // Encode assembles the operands into the 4 little-endian bytes of the