feat(arch): the SVE multiple-structure loads and stores
Assisted-by: GLM 5.3 Flash
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@@ -235,6 +235,12 @@ type ExtOperand struct {
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// the destinations of the entries that carry Er or Sae accept it. The
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// arm64 entries all carry the zero value.
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Round ExtRounding
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// List carries the register count of a multi-vector list operand, the
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// [Z13.B, Z14.B, Z15.B] shape of the SVE LD2-LD4 and ST2-ST4
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// multiple-structure loads and stores: consecutive registers under one
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// arrangement, of which the encoding carries the first alone. A list
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// of one register carries 0, and the amd64 operands never more.
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List int
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}
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// ExtVector builds a scalable vector operand, ADD Z1.S style.
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@@ -3486,6 +3492,106 @@ var arm64Extensions = []ExtInstr{
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{Name: "ZBFSUB", Summary: "Subtract BFloat16 halfwords, unpredicated",
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Word: 0x65000400, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFSUB; inst_gen.go + arm64sveenc.s"},
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// --- the SVE multiple-structure loads and stores --------------------------
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//
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// The two-, three- and four-register list loads and stores over the
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// two-general-register addressing mode, the shift scaling the base by
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// the list element size. The list operand carries consecutive
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// registers under one arrangement; the encoding takes the first alone
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// and the conversion validates the rest against the instruction's own
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// digit. The MUL VL immediate-offset variant of the same shapes stays
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// unwired. Provenance as above: the toolchain encoding table and its
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// generated corpus, both produced from Arm's official ISA description.
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{Name: "ZLD2B", Summary: "Load 2 scalable vector registers, .B list",
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Word: 0xa420c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD2B (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD2D", Summary: "Load 2 scalable vector registers, .D list",
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Word: 0xa5a0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD2D (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD2H", Summary: "Load 2 scalable vector registers, .H list",
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Word: 0xa4a0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD2H (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD2Q", Summary: "Load 2 scalable vector registers, .Q list",
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Word: 0xa4a08000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD2Q (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD2W", Summary: "Load 2 scalable vector registers, .W list",
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Word: 0xa520c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD2W (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD3B", Summary: "Load 3 scalable vector registers, .B list",
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Word: 0xa440c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD3B (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD3D", Summary: "Load 3 scalable vector registers, .D list",
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Word: 0xa5c0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD3D (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD3H", Summary: "Load 3 scalable vector registers, .H list",
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Word: 0xa4c0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD3H (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD3Q", Summary: "Load 3 scalable vector registers, .Q list",
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Word: 0xa5208000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD3Q (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD3W", Summary: "Load 3 scalable vector registers, .W list",
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Word: 0xa540c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD3W (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD4B", Summary: "Load 4 scalable vector registers, .B list",
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Word: 0xa460c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD4B (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD4D", Summary: "Load 4 scalable vector registers, .D list",
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Word: 0xa5e0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD4D (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD4H", Summary: "Load 4 scalable vector registers, .H list",
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Word: 0xa4e0c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD4H (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD4Q", Summary: "Load 4 scalable vector registers, .Q list",
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Word: 0xa5a08000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD4Q (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZLD4W", Summary: "Load 4 scalable vector registers, .W list",
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Word: 0xa560c000, Form: ExtFormSveLoad, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZLD4W (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST2B", Summary: "Store 2 scalable vector registers, .B list",
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Word: 0xe4206000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST2B (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST2D", Summary: "Store 2 scalable vector registers, .D list",
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Word: 0xe5a06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST2D (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST2H", Summary: "Store 2 scalable vector registers, .H list",
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Word: 0xe4a06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST2H (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST2Q", Summary: "Store 2 scalable vector registers, .Q list",
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Word: 0xe4600000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST2Q (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST2W", Summary: "Store 2 scalable vector registers, .W list",
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Word: 0xe5206000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST2W (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST3B", Summary: "Store 3 scalable vector registers, .B list",
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Word: 0xe4406000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST3B (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST3D", Summary: "Store 3 scalable vector registers, .D list",
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Word: 0xe5c06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST3D (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST3H", Summary: "Store 3 scalable vector registers, .H list",
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Word: 0xe4c06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST3H (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST3Q", Summary: "Store 3 scalable vector registers, .Q list",
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Word: 0xe4a00000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST3Q (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST3W", Summary: "Store 3 scalable vector registers, .W list",
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Word: 0xe5406000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST3W (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST4B", Summary: "Store 4 scalable vector registers, .B list",
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Word: 0xe4606000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 0, Arr: ExtArrB, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST4B (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST4D", Summary: "Store 4 scalable vector registers, .D list",
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Word: 0xe5e06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 3, Arr: ExtArrD, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST4D (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST4H", Summary: "Store 4 scalable vector registers, .H list",
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Word: 0xe4e06000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 1, Arr: ExtArrH, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST4H (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST4Q", Summary: "Store 4 scalable vector registers, .Q list",
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Word: 0xe4e00000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 4, Arr: ExtArrQ, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST4Q (multiple structures); inst_gen.go + arm64sveenc.s"},
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{Name: "ZST4W", Summary: "Store 4 scalable vector registers, .W list",
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Word: 0xe5606000, Form: ExtFormSveStore, SveMode: extMemPair, SveShift: 2, Arr: ExtArrS, Feature: ExtFeatureSVE,
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Ref: "ARM DDI 0487J: ZST4W (multiple structures); inst_gen.go + arm64sveenc.s"},
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// --- the SVE2 crypto family ----------------------------------------------
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//
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@@ -1551,6 +1551,16 @@ func TestArm64ExtStage4Golden(t *testing.T) {
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{"ZBFSUB Z7.H, Z6.H, Z23.H", "ZBFSUB", ExtFormVectorsZm, ExtQualNone, ExtArrH,
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[]ExtOperand{ExtVector(7, ExtArrH), ExtVector(6, ExtArrH), ExtVector(23, ExtArrH)},
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0x650704d7},
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// The multiple-structure loads and stores.
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{"ZLD2B (R6)(R14), P4.Z, [Z13.B, Z14.B]", "ZLD2B", ExtFormSveLoad, ExtQualNone, ExtArrB,
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[]ExtOperand{ExtSveMemPair(6, 0, 14, false), ExtPredicate(4, ExtQualZeroing), ExtOperand{Kind: ExtZReg, Reg: 13, Arr: ExtArrB, List: 2}},
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0xa426d1cd},
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{"ZLD4D (R6<<3)(R14), P4.Z, [Z13.D, Z14.D, Z15.D, Z16.D]", "ZLD4D", ExtFormSveLoad, ExtQualNone, ExtArrD,
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[]ExtOperand{ExtSveMemPair(6, 3, 14, false), ExtPredicate(4, ExtQualZeroing), ExtOperand{Kind: ExtZReg, Reg: 13, Arr: ExtArrD, List: 4}},
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0xa5e6d1cd},
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{"ZST2Q [Z8.Q, Z9.Q], P3, (R6<<4)(RSP)", "ZST2Q", ExtFormSveStore, ExtQualNone, ExtArrQ,
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[]ExtOperand{ExtOperand{Kind: ExtZReg, Reg: 8, Arr: ExtArrQ, List: 2}, ExtPredicateSized(3, ExtArrNone), ExtSveMemPair(6, 4, 31, true)},
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0xe4660fe8},
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} {
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in := extInstructionMeta(t, tt.mnem, tt.form, tt.qual, tt.arr)
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got, err := in.Encode(tt.ops)
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