feat(arch): add the amd64 fp16 packed imm8-control group
Assisted-by: GLM 5.3
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+81
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@@ -10,11 +10,12 @@
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//
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// The families are AVX512-BF16, AVX512-VP2INTERSECT and AVX512-FP16, the
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// latter's scalar core with its imm8-control group, its packed 512-bit and
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// VL arithmetic, the embedded rounding of its FP operations and its fourteen
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// packed conversion directions, in their EVEX register forms. The encodings
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// are transcribed from the SDM instruction entries and cross-checked against
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// binutils-gdb's assembler testsuite; the golden vectors in amd64_ext_test.go
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// pin the bytes. VPOPCNTD and VPOPCNTQ, the third family of the 2026-09-19
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// VL arithmetic, the packed mirror of the imm8-control group, the embedded
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// rounding of its FP operations and its fourteen packed conversion
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// directions, in their EVEX register forms. The encodings are transcribed
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// from the SDM instruction entries and cross-checked against binutils-gdb's
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// assembler testsuite; the golden vectors in amd64_ext_test.go pin the
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// bytes. VPOPCNTD and VPOPCNTQ, the third family of the 2026-09-19
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// survey, no longer belong here: the Go toolchain's assembler knows them
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// today, they live in the generated table and the EVEX encoder, and a
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// mnemonic the toolchain has is not an extension. VCVTPS2PH, VCVTUDQ2PS
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@@ -482,6 +483,8 @@ func (in ExtInstr) encodeAmd64(ops []ExtOperand) ([]byte, error) {
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return in.encodeAmdVec3Imm(ops)
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case ExtFormAmdMask2Imm:
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return in.encodeAmdMask2Imm(ops)
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case ExtFormAmdVec2Imm:
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return in.encodeAmdVec2Imm(ops)
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default:
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return nil, fmt.Errorf("%s: unknown form %d", in.Name, in.Form)
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}
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@@ -711,6 +714,43 @@ func (in ExtInstr) encodeAmdVec3Imm(ops []ExtOperand) ([]byte, error) {
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return append(out, imm), nil
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}
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// encodeAmdVec2Imm fills the two-vector form with a control immediate: imm,
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// src, dest, the packed imm8-control group. An entry with Mem set takes the
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// memory shape of the source, zmm2/m512 in the manual; the control byte
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// rides after the ModR/M and its displacement bytes, the last byte of the
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// word.
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func (in ExtInstr) encodeAmdVec2Imm(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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imm, err := in.amd64Imm8(ops[0], 1)
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if err != nil {
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return nil, err
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}
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dest, mask, zeroing, _, err := in.amd64WriteMask(ops[2], 3)
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if err != nil {
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return nil, err
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}
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if in.Mem == 2 && ops[1].Kind == ExtMem {
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if err := in.amd64Vector(dest, class, 3); err != nil {
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return nil, err
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}
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out, err := in.amd64MemBytes(in.Bytes, dest.Reg, -1, ops[1], 2)
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if err != nil {
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return nil, err
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}
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amd64ApplyMask(out, mask, zeroing)
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return append(out, imm), nil
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}
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if err := in.amd64Vector(ops[1], class, 2); err != nil {
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return nil, err
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}
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if err := in.amd64Vector(dest, class, 3); err != nil {
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return nil, err
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}
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out := amd64Encode(in.Bytes, dest.Reg, -1, ops[1].Reg)
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amd64ApplyMask(out, mask, zeroing)
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return append(out, imm), nil
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}
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// encodeAmdMask2Imm fills the opmask-destination form with a control
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// immediate: imm, src1, src2, dest. An entry with Mem set takes the memory
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// shape of the second source.
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@@ -1313,4 +1353,40 @@ var amd64Extensions = []ExtInstr{
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{Name: "VCVTPD2PH", Summary: "Convert packed double-precision values to packed FP16 values, quarter-width destination",
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Bytes: []byte{0x62, 0x05, 0x85, 0x00, 0x5A, 0xC0}, Form: ExtFormAmdVec2ToQuarter, Mem: 1, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VCVTPD2PH (EVEX.128.66.MAP5.W1 5A /r, XMM destination)"},
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// AVX512-FP16 packed, the imm8-control group: the packed mirror of the
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// scalar core's mantissa extraction, reduction and rounding to fraction
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// bits, one control byte over every lane of the vector. The controls
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// share the immediate layouts and the tables the scalar entries carry,
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// ExtImm8ScaleRound and ExtImm8GetMant, the reserved upper nibble of the
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// mantissa control refused rather than encoded. The sources read from
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// memory full-width, no broadcast: the control governs the lanes, not a
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// splatted element.
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{Name: "VRNDSCALEPH", Summary: "Round packed FP16 values to imm8 fraction bits under an imm8 round control",
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Bytes: []byte{0x62, 0x03, 0x04, 0x40, 0x08, 0xC0}, Form: ExtFormAmdVec2Imm, Mem: 2, Mask: true, Imm8: ExtImm8ScaleRound, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VRNDSCALEPH (EVEX.512.NP.0F3A.W0 08 /r /ib)"},
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{Name: "VRNDSCALEPH", Summary: "Round packed FP16 values to imm8 fraction bits under an imm8 round control",
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Bytes: []byte{0x62, 0x03, 0x04, 0x20, 0x08, 0xC0}, Form: ExtFormAmdVec2Imm, Mem: 2, Mask: true, Imm8: ExtImm8ScaleRound, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VRNDSCALEPH (EVEX.256.NP.0F3A.W0 08 /r /ib)"},
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{Name: "VRNDSCALEPH", Summary: "Round packed FP16 values to imm8 fraction bits under an imm8 round control",
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Bytes: []byte{0x62, 0x03, 0x04, 0x00, 0x08, 0xC0}, Form: ExtFormAmdVec2Imm, Mem: 2, Mask: true, Imm8: ExtImm8ScaleRound, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VRNDSCALEPH (EVEX.128.NP.0F3A.W0 08 /r /ib)"},
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{Name: "VREDUCEPH", Summary: "Reduce packed FP16 values by imm8 fraction bits under an imm8 round control",
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Bytes: []byte{0x62, 0x03, 0x04, 0x40, 0x56, 0xC0}, Form: ExtFormAmdVec2Imm, Mem: 2, Mask: true, Imm8: ExtImm8ScaleRound, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VREDUCEPH (EVEX.512.NP.0F3A.W0 56 /r /ib)"},
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{Name: "VREDUCEPH", Summary: "Reduce packed FP16 values by imm8 fraction bits under an imm8 round control",
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Bytes: []byte{0x62, 0x03, 0x04, 0x20, 0x56, 0xC0}, Form: ExtFormAmdVec2Imm, Mem: 2, Mask: true, Imm8: ExtImm8ScaleRound, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VREDUCEPH (EVEX.256.NP.0F3A.W0 56 /r /ib)"},
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{Name: "VREDUCEPH", Summary: "Reduce packed FP16 values by imm8 fraction bits under an imm8 round control",
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Bytes: []byte{0x62, 0x03, 0x04, 0x00, 0x56, 0xC0}, Form: ExtFormAmdVec2Imm, Mem: 2, Mask: true, Imm8: ExtImm8ScaleRound, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VREDUCEPH (EVEX.128.NP.0F3A.W0 56 /r /ib)"},
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{Name: "VGETMANTPH", Summary: "Extract the normalised mantissas of packed FP16 values under an imm8 control",
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Bytes: []byte{0x62, 0x03, 0x04, 0x40, 0x26, 0xC0}, Form: ExtFormAmdVec2Imm, Mem: 2, Mask: true, Imm8: ExtImm8GetMant, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VGETMANTPH (EVEX.512.NP.0F3A.W0 26 /r /ib)"},
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{Name: "VGETMANTPH", Summary: "Extract the normalised mantissas of packed FP16 values under an imm8 control",
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Bytes: []byte{0x62, 0x03, 0x04, 0x20, 0x26, 0xC0}, Form: ExtFormAmdVec2Imm, Mem: 2, Mask: true, Imm8: ExtImm8GetMant, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VGETMANTPH (EVEX.256.NP.0F3A.W0 26 /r /ib)"},
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{Name: "VGETMANTPH", Summary: "Extract the normalised mantissas of packed FP16 values under an imm8 control",
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Bytes: []byte{0x62, 0x03, 0x04, 0x00, 0x26, 0xC0}, Form: ExtFormAmdVec2Imm, Mem: 2, Mask: true, Imm8: ExtImm8GetMant, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VGETMANTPH (EVEX.128.NP.0F3A.W0 26 /r /ib)"},
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}
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+58
-2
@@ -1050,6 +1050,56 @@ var amd64GoldenRows = []amd64GoldenRow{
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{"vcvtsh2usi 64-bit memory source disp8", "VCVTSH2USI",
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[]ExtOperand{ExtMemory(1, 1), ExtGpr64(12)},
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"6275fe08796101", "62 75 fe 08 79 61 01 vcvtsh2usi 0x2(%rcx),%r12 (Disp8(01))"},
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// The packed imm8-control group, the packed mirror of the scalar core's
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// mantissa extraction, reduction and rounding. The control byte leads,
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// the sources read from memory full-width, and the immediate layouts are
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// the ones the scalar rows share: every row takes the $0x7b the suite
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// drives through the fraction-bit forms, save VGETMANTPH, whose reserved
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// upper nibble the layer refuses and whose $0x0b encodes the same opcode
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// row the suite's $0x7b spells.
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{"vrndscaleph zmm", "VRNDSCALEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtZmm(5), ExtZmm(6)},
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"62f37c4808f57b", "62 f3 7c 48 08 f5 7b vrndscaleph $0x7b,%zmm5,%zmm6"},
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{"vrndscaleph ymm", "VRNDSCALEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtYmm(5), ExtYmm(6)},
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"62f37c2808f57b", "62 f3 7c 28 08 f5 7b vrndscaleph $0x7b,%ymm5,%ymm6"},
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{"vrndscaleph xmm", "VRNDSCALEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtXmm(5), ExtXmm(6)},
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"62f37c0808f57b", "62 f3 7c 08 08 f5 7b vrndscaleph $0x7b,%xmm5,%xmm6"},
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{"vreduceph zmm", "VREDUCEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtZmm(5), ExtZmm(6)},
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"62f37c4856f57b", "62 f3 7c 48 56 f5 7b vreduceph $0x7b,%zmm5,%zmm6"},
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{"vreduceph ymm", "VREDUCEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtYmm(5), ExtYmm(6)},
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"62f37c2856f57b", "62 f3 7c 28 56 f5 7b vreduceph $0x7b,%ymm5,%ymm6"},
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{"vreduceph xmm", "VREDUCEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtXmm(5), ExtXmm(6)},
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"62f37c0856f57b", "62 f3 7c 08 56 f5 7b vreduceph $0x7b,%xmm5,%xmm6"},
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{"vgetmantph zmm", "VGETMANTPH",
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[]ExtOperand{ExtImmediate(0x0b), ExtZmm(5), ExtZmm(6)},
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"62f37c4826f50b", "62 f3 7c 48 26 f5 0b vgetmantph $0xb,%zmm5,%zmm6"},
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{"vgetmantph ymm", "VGETMANTPH",
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[]ExtOperand{ExtImmediate(0x0b), ExtYmm(5), ExtYmm(6)},
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"62f37c2826f50b", "62 f3 7c 28 26 f5 0b vgetmantph $0xb,%ymm5,%ymm6"},
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{"vgetmantph xmm", "VGETMANTPH",
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[]ExtOperand{ExtImmediate(0x0b), ExtXmm(5), ExtXmm(6)},
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"62f37c0826f50b", "62 f3 7c 08 26 f5 0b vgetmantph $0xb,%xmm5,%xmm6"},
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{"vrndscaleph memory source", "VRNDSCALEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtMemory(9, 0), ExtZmm(30)},
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"62437c4808317b", "62 43 7c 48 08 31 7b vrndscaleph $0x7b,(%r9),%zmm30"},
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{"vrndscaleph memory source disp8", "VRNDSCALEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtMemory(1, 127), ExtZmm(6)},
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"62f37c4808717f7b", "62 f3 7c 48 08 71 7f 7b vrndscaleph $0x7b,0x1fc0(%rcx),%zmm6 (Disp8(7f))"},
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{"vreduceph memory source", "VREDUCEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtMemory(9, 0), ExtZmm(30)},
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"62437c4856317b", "62 43 7c 48 56 31 7b vreduceph $0x7b,(%r9),%zmm30"},
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{"vgetmantph memory source", "VGETMANTPH",
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[]ExtOperand{ExtImmediate(0x0b), ExtMemory(9, 0), ExtZmm(30)},
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"62437c4826310b", "62 43 7c 48 26 31 0b vgetmantph $0xb,(%r9),%zmm30"},
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{"vrndscaleph k7 zeroing", "VRNDSCALEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtZmm(5), ExtWriteMasked(ExtZmm(6), 7, true)},
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"62f37ccf08f57b", "62 f3 7c cf 08 f5 7b vrndscaleph $0x7b,%zmm5,%zmm6{%k7}{z}"},
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}
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// amd64ResolveEntry finds the table entry a golden row exercises: the entry
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@@ -1374,6 +1424,12 @@ func TestAmd64ExtRejects(t *testing.T) {
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{"broadcast on the full-width FP16 source", "VCVTPH2W",
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[]ExtOperand{ExtBroadcast(9, 0), ExtZmm(30)},
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"the entry's memory operand takes none"},
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{"broadcast on the packed control form's source", "VRNDSCALEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtBroadcast(9, 0), ExtZmm(30)},
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"the entry's memory operand takes none"},
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{"reserved upper nibble on the packed mantissa control", "VGETMANTPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtZmm(5), ExtZmm(6)},
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"reserved and must be zero"},
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} {
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in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
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_, err := in.Encode(tt.ops)
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@@ -1518,7 +1574,7 @@ func TestAmd64ExtArchBinding(t *testing.T) {
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t.Errorf("Extensions(%s) carries %d instructions, want none", a, len(got))
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}
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}
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if got := Extensions(AMD64); len(got) != 112 {
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t.Errorf("the amd64 layer registers %d instructions, want 112", len(got))
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if got := Extensions(AMD64); len(got) != 121 {
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t.Errorf("the amd64 layer registers %d instructions, want 121", len(got))
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}
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}
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+11
-1
@@ -480,6 +480,11 @@ const (
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// where dest is an opmask register and the immediate's layout is named
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// by the entry's Imm8 kind.
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ExtFormAmdMask2Imm
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// ExtFormAmdVec2Imm is the two-vector form with a control immediate,
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// VRNDSCALEPH $0x7b, Z5, Z6 style: the immediate leads, the order the
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// reference listings write it in. Operands: imm, src, dest, and the
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// immediate's layout is named by the entry's Imm8 kind.
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ExtFormAmdVec2Imm
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// ExtFormAmdMemVec is the memory-load form: VMOVSH X30, 4660(R8) shape,
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// the manual's xmm1, m16 lines that stand beside the register form.
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// Operands: mem, dest.
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@@ -685,6 +690,8 @@ func (f ExtForm) Arity() int {
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return 2
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case ExtFormAmdVec3Imm, ExtFormAmdMask2Imm:
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return 4
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case ExtFormAmdVec2Imm:
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return 3
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case ExtFormAmdMemVec, ExtFormAmdVecMem:
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return 2
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case ExtFormPredicateOne, ExtFormPredicateWrite, ExtFormPredicateCounter:
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@@ -808,6 +815,8 @@ func (f ExtForm) String() string {
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return "immediate, three vectors"
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case ExtFormAmdMask2Imm:
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return "immediate, two vectors into an opmask"
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case ExtFormAmdVec2Imm:
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return "immediate and two vectors"
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case ExtFormAmdMemVec:
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return "memory into a vector"
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case ExtFormAmdVecMem:
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@@ -1057,7 +1066,8 @@ func (in ExtInstr) Encode(ops []ExtOperand) ([]byte, error) {
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case ExtFormAmdVec3, ExtFormAmdVec2, ExtFormAmdVec2Half, ExtFormAmdMask2,
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ExtFormAmdVecGprVec, ExtFormAmdGprVec, ExtFormAmdVecGpr,
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ExtFormAmdVec3Imm, ExtFormAmdMask2Imm, ExtFormAmdMemVec, ExtFormAmdVecMem,
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ExtFormAmdVec2Wide, ExtFormAmdVec2Quarter, ExtFormAmdVec2ToQuarter:
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ExtFormAmdVec2Wide, ExtFormAmdVec2Quarter, ExtFormAmdVec2ToQuarter,
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ExtFormAmdVec2Imm:
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return in.encodeAmd64(ops)
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case ExtFormPredicateLogical, ExtFormPredicateSelect:
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return in.encodePredicateLogical(ops)
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