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feat(arch): add the amd64 fp16 packed imm8-control group

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Assisted-by: GLM 5.3
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petrbalvin committed 2026-10-07 13:51:48 +02:00
1 parent 8de1b371da
commit d03de62c07
4 files changed
+158 -10
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arch/amd64_ext_test.go
+58 -2
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@@ -1050,6 +1050,56 @@ var amd64GoldenRows = []amd64GoldenRow{
{"vcvtsh2usi 64-bit memory source disp8", "VCVTSH2USI",
[]ExtOperand{ExtMemory(1, 1), ExtGpr64(12)},
"6275fe08796101", "62 75 fe 08 79 61 01 vcvtsh2usi 0x2(%rcx),%r12 (Disp8(01))"},
// The packed imm8-control group, the packed mirror of the scalar core's
// mantissa extraction, reduction and rounding. The control byte leads,
// the sources read from memory full-width, and the immediate layouts are
// the ones the scalar rows share: every row takes the $0x7b the suite
// drives through the fraction-bit forms, save VGETMANTPH, whose reserved
// upper nibble the layer refuses and whose $0x0b encodes the same opcode
// row the suite's $0x7b spells.
{"vrndscaleph zmm", "VRNDSCALEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtZmm(5), ExtZmm(6)},
"62f37c4808f57b", "62 f3 7c 48 08 f5 7b vrndscaleph $0x7b,%zmm5,%zmm6"},
{"vrndscaleph ymm", "VRNDSCALEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtYmm(5), ExtYmm(6)},
"62f37c2808f57b", "62 f3 7c 28 08 f5 7b vrndscaleph $0x7b,%ymm5,%ymm6"},
{"vrndscaleph xmm", "VRNDSCALEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtXmm(5), ExtXmm(6)},
"62f37c0808f57b", "62 f3 7c 08 08 f5 7b vrndscaleph $0x7b,%xmm5,%xmm6"},
{"vreduceph zmm", "VREDUCEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtZmm(5), ExtZmm(6)},
"62f37c4856f57b", "62 f3 7c 48 56 f5 7b vreduceph $0x7b,%zmm5,%zmm6"},
{"vreduceph ymm", "VREDUCEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtYmm(5), ExtYmm(6)},
"62f37c2856f57b", "62 f3 7c 28 56 f5 7b vreduceph $0x7b,%ymm5,%ymm6"},
{"vreduceph xmm", "VREDUCEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtXmm(5), ExtXmm(6)},
"62f37c0856f57b", "62 f3 7c 08 56 f5 7b vreduceph $0x7b,%xmm5,%xmm6"},
{"vgetmantph zmm", "VGETMANTPH",
[]ExtOperand{ExtImmediate(0x0b), ExtZmm(5), ExtZmm(6)},
"62f37c4826f50b", "62 f3 7c 48 26 f5 0b vgetmantph $0xb,%zmm5,%zmm6"},
{"vgetmantph ymm", "VGETMANTPH",
[]ExtOperand{ExtImmediate(0x0b), ExtYmm(5), ExtYmm(6)},
"62f37c2826f50b", "62 f3 7c 28 26 f5 0b vgetmantph $0xb,%ymm5,%ymm6"},
{"vgetmantph xmm", "VGETMANTPH",
[]ExtOperand{ExtImmediate(0x0b), ExtXmm(5), ExtXmm(6)},
"62f37c0826f50b", "62 f3 7c 08 26 f5 0b vgetmantph $0xb,%xmm5,%xmm6"},
{"vrndscaleph memory source", "VRNDSCALEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtMemory(9, 0), ExtZmm(30)},
"62437c4808317b", "62 43 7c 48 08 31 7b vrndscaleph $0x7b,(%r9),%zmm30"},
{"vrndscaleph memory source disp8", "VRNDSCALEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtMemory(1, 127), ExtZmm(6)},
"62f37c4808717f7b", "62 f3 7c 48 08 71 7f 7b vrndscaleph $0x7b,0x1fc0(%rcx),%zmm6 (Disp8(7f))"},
{"vreduceph memory source", "VREDUCEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtMemory(9, 0), ExtZmm(30)},
"62437c4856317b", "62 43 7c 48 56 31 7b vreduceph $0x7b,(%r9),%zmm30"},
{"vgetmantph memory source", "VGETMANTPH",
[]ExtOperand{ExtImmediate(0x0b), ExtMemory(9, 0), ExtZmm(30)},
"62437c4826310b", "62 43 7c 48 26 31 0b vgetmantph $0xb,(%r9),%zmm30"},
{"vrndscaleph k7 zeroing", "VRNDSCALEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtZmm(5), ExtWriteMasked(ExtZmm(6), 7, true)},
"62f37ccf08f57b", "62 f3 7c cf 08 f5 7b vrndscaleph $0x7b,%zmm5,%zmm6{%k7}{z}"},
}
// amd64ResolveEntry finds the table entry a golden row exercises: the entry
@@ -1374,6 +1424,12 @@ func TestAmd64ExtRejects(t *testing.T) {
{"broadcast on the full-width FP16 source", "VCVTPH2W",
[]ExtOperand{ExtBroadcast(9, 0), ExtZmm(30)},
"the entry's memory operand takes none"},
{"broadcast on the packed control form's source", "VRNDSCALEPH",
[]ExtOperand{ExtImmediate(0x7b), ExtBroadcast(9, 0), ExtZmm(30)},
"the entry's memory operand takes none"},
{"reserved upper nibble on the packed mantissa control", "VGETMANTPH",
[]ExtOperand{ExtImmediate(0x7b), ExtZmm(5), ExtZmm(6)},
"reserved and must be zero"},
} {
in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
_, err := in.Encode(tt.ops)
@@ -1518,7 +1574,7 @@ func TestAmd64ExtArchBinding(t *testing.T) {
t.Errorf("Extensions(%s) carries %d instructions, want none", a, len(got))
}
}
if got := Extensions(AMD64); len(got) != 112 {
t.Errorf("the amd64 layer registers %d instructions, want 112", len(got))
if got := Extensions(AMD64); len(got) != 121 {
t.Errorf("the amd64 layer registers %d instructions, want 121", len(got))
}
}