feat(arch): add the scalar FP16 memory forms to the amd64 extension layer
Assisted-by: GLM 5.3 Flash
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petrbalvin committed
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@@ -18,9 +18,11 @@
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// live in the generated table and the EVEX encoder, and a mnemonic the
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// toolchain has is not an extension.
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//
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// Memory operands, write masking ({k1}{z}) and embedded rounding arrive with
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// a later slice; every form here encodes the unmasked register forms, which
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// is what the golden-vector path exercises.
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// The forms encode the unmasked shapes: register forms throughout, and the
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// scalar FP16 memory forms beside them, base-relative operands with the
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// ModR/M disp8 and disp32 choices and the SIB byte RSP and R12 demand. A
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// scaled index, write masking ({k1}{z}) and embedded rounding still arrive
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// with a later slice.
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package arch
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@@ -196,7 +198,11 @@ func (in ExtInstr) amd64PlainReg(op ExtOperand, max, pos int) error {
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// amd64Vector checks one vector operand against the class the entry encodes.
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func (in ExtInstr) amd64Vector(op ExtOperand, class ExtOperandKind, pos int) error {
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if op.Kind != class {
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return fmt.Errorf("%s: operand %d wants a %s, got %s", in.Name, pos, class, op.Kind)
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article := "a"
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if class == ExtXMM {
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article = "an"
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}
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return fmt.Errorf("%s: operand %d wants %s %s, got %s", in.Name, pos, article, class, op.Kind)
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}
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return in.amd64PlainReg(op, 31, pos)
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}
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@@ -234,6 +240,10 @@ func (in ExtInstr) encodeAmd64(ops []ExtOperand) ([]byte, error) {
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return in.encodeAmdVecGprVec(ops)
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case ExtFormAmdGprVec, ExtFormAmdVecGpr:
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return in.encodeAmdGprPair(ops)
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case ExtFormAmdMemVec:
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return in.encodeAmdMemVec(ops)
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case ExtFormAmdVecMem:
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return in.encodeAmdVecMem(ops)
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case ExtFormAmdVec3Imm:
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return in.encodeAmdVec3Imm(ops)
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case ExtFormAmdMask2Imm:
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@@ -244,17 +254,66 @@ func (in ExtInstr) encodeAmd64(ops []ExtOperand) ([]byte, error) {
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}
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// encodeAmdVec3 fills the non-destructive three-vector form: src1, src2,
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// dest, all under one register class.
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// dest, all under one register class. An entry with Mem set takes the
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// memory shape of that position too: the second source of the scalar
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// arithmetic, spelled xmm3/m16 in the manual, may be a base-relative
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// operand, which rides the r/m field with its displacement bytes after the
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// opcode.
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func (in ExtInstr) encodeAmdVec3(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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for i, op := range ops {
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if err := in.amd64Vector(op, class, i+1); err != nil {
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if err := in.amd64Vector(ops[0], class, 1); err != nil {
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return nil, err
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}
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if in.Mem == 2 && ops[1].Kind == ExtMem {
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base, disp, err := in.amd64Memory(ops[1], 2)
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if err != nil {
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return nil, err
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}
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if err := in.amd64Vector(ops[2], class, 3); err != nil {
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return nil, err
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}
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return amd64EncodeMemory(in.Bytes, ops[2].Reg, ops[0].Reg, base, disp), nil
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}
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for i, op := range ops[1:] {
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if err := in.amd64Vector(op, class, i+2); err != nil {
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return nil, err
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}
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}
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return amd64Encode(in.Bytes, ops[2].Reg, ops[0].Reg, ops[1].Reg), nil
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}
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// encodeAmdMemVec fills the memory-load form: mem, dest. VMOVSH X30,
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// 4660(R8) shape, the manual's xmm1, m16 lines beside the register form.
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// The form reads one value from memory, so the third register slot stays
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// unused, which the encoding spells as vvvv 1111.
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func (in ExtInstr) encodeAmdMemVec(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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base, disp, err := in.amd64Memory(ops[0], 1)
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if err != nil {
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return nil, err
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}
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if err := in.amd64Vector(ops[1], class, 2); err != nil {
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return nil, err
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}
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return amd64EncodeMemory(in.Bytes, ops[1].Reg, -1, base, disp), nil
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}
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// encodeAmdVecMem fills the memory-store form: src, mem. VMOVSH 4660(R9),
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// X29 shape, the manual's m16, xmm1 lines. The register source sits in the
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// ModR/M reg field and the memory destination in r/m, and vvvv stays
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// unused.
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func (in ExtInstr) encodeAmdVecMem(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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if err := in.amd64Vector(ops[0], class, 1); err != nil {
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return nil, err
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}
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base, disp, err := in.amd64Memory(ops[1], 2)
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if err != nil {
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return nil, err
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}
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return amd64EncodeMemory(in.Bytes, ops[0].Reg, -1, base, disp), nil
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}
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// encodeAmdVec2 fills the two-vector form: src, dest. The half form narrows
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// the destination: VCVTNEPS2BF16 converts 512 bits of source into 256 bits
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// of destination, and at 128 bits the companion stays the class itself.
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@@ -500,32 +559,44 @@ var amd64Extensions = []ExtInstr{
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{Name: "VMOVSH", Summary: "Move a scalar FP16 value",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x10, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VMOVSH (EVEX.NDS.LIG.F3.MAP5.W0 10 /r)"},
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{Name: "VMOVSH", Summary: "Move a scalar FP16 value from memory into an XMM register",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x10, 0xC0}, Form: ExtFormAmdMemVec, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VMOVSH (EVEX.LIG.F3.MAP5.W0 10 /r, m16 source)"},
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{Name: "VMOVSH", Summary: "Move a scalar FP16 value from an XMM register to memory",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x11, 0xC0}, Form: ExtFormAmdVecMem, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VMOVSH (EVEX.LIG.F3.MAP5.W0 11 /r, m16 destination)"},
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{Name: "VMOVW", Summary: "Move a word between a general register and an XMM register",
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Bytes: []byte{0x62, 0x05, 0x05, 0x00, 0x6E, 0xC0}, Form: ExtFormAmdGprVec, Feature: ExtFeatureFP16, Wig: true,
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Ref: "Intel SDM Vol. 2C, VMOVW (EVEX.128.66.MAP5.WIG 6E /r)"},
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{Name: "VMOVW", Summary: "Move a word between an XMM register and a general register",
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Bytes: []byte{0x62, 0x05, 0x05, 0x00, 0x7E, 0xC0}, Form: ExtFormAmdVecGpr, Feature: ExtFeatureFP16, Wig: true,
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Ref: "Intel SDM Vol. 2C, VMOVW (EVEX.128.66.MAP5.WIG 7E /r)"},
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{Name: "VMOVW", Summary: "Move a word from memory into an XMM register",
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Bytes: []byte{0x62, 0x05, 0x05, 0x00, 0x6E, 0xC0}, Form: ExtFormAmdMemVec, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VMOVW (EVEX.128.66.MAP5.WIG 6E /r, m16 source)"},
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{Name: "VMOVW", Summary: "Move a word from an XMM register to memory",
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Bytes: []byte{0x62, 0x05, 0x05, 0x00, 0x7E, 0xC0}, Form: ExtFormAmdVecMem, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VMOVW (EVEX.128.66.MAP5.WIG 7E /r, m16 destination)"},
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{Name: "VADDSH", Summary: "Add scalar FP16 values",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x58, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x58, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VADDSH (EVEX.NDS.LIG.F3.MAP5.W0 58 /r)"},
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{Name: "VSUBSH", Summary: "Subtract scalar FP16 values",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5C, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5C, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VSUBSH (EVEX.NDS.LIG.F3.MAP5.W0 5C /r)"},
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{Name: "VMULSH", Summary: "Multiply scalar FP16 values",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x59, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x59, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VMULSH (EVEX.NDS.LIG.F3.MAP5.W0 59 /r)"},
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{Name: "VDIVSH", Summary: "Divide scalar FP16 values",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5E, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5E, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VDIVSH (EVEX.NDS.LIG.F3.MAP5.W0 5E /r)"},
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{Name: "VMINSH", Summary: "Return the minimum of scalar FP16 values",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5D, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5D, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VMINSH (EVEX.NDS.LIG.F3.MAP5.W0 5D /r)"},
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{Name: "VMAXSH", Summary: "Return the maximum of scalar FP16 values",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5F, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5F, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VMAXSH (EVEX.NDS.LIG.F3.MAP5.W0 5F /r)"},
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{Name: "VSQRTSH", Summary: "Compute the square root of a scalar FP16 value",
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x51, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
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Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x51, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
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Ref: "Intel SDM Vol. 2C, VSQRTSH (EVEX.NDS.LIG.F3.MAP5.W0 51 /r)"},
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{Name: "VSCALEFSH", Summary: "Scale a scalar FP16 value by the ratio of two others",
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Bytes: []byte{0x62, 0x06, 0x05, 0x00, 0x2D, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
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