feat(arch): add the scalar FP16 memory forms to the amd64 extension layer
Assisted-by: GLM 5.3 Flash
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@@ -264,6 +264,75 @@ var amd64GoldenRows = []amd64GoldenRow{
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[]ExtOperand{ExtImmediate(0x7b), ExtXmm(29), ExtXmm(28), ExtXmm(30)},
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"620314000af47b", "62 03 14 00 0a f4 7b vrndscalesh $0x7b,%xmm28,%xmm29,%xmm30"},
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// The memory forms of the scalar moves and arithmetic, against the same
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// listings' memory rows. The zero-displacement rows match the GNU
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// source spellings outright and every base R8+ row exercises the EVEX.B
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// high-base bit. The disp8 rows pin the bytes the listing lays down;
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// binutils mainline encodes EVEX displacements with the APX disp8*N
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// scaling, so its source spellings (0xfe for the m16 rows, 0x1fc0 for
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// the m512 ones) are N times the plain SDM displacement those bytes
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// carry, and the operand lists here hold the plain displacement. The
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// rows with no GNU line are derived: the disp32 form the SDM ModR/M
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// table defines and the source listings never emit plain, and the SIB
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// byte the R12 base demands.
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{"vmovsh load from r9", "VMOVSH",
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[]ExtOperand{ExtMemory(9, 0), ExtXmm(30)},
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"62457e081031", "62 45 7e 08 10 31 vmovsh (%r9),%xmm30"},
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{"vmovsh load disp8", "VMOVSH",
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[]ExtOperand{ExtMemory(1, 127), ExtXmm(30)},
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"62657e0810717f", "62 65 7e 08 10 71 7f vmovsh 0xfe(%rcx),%xmm30 (Disp8(7f))"},
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{"vmovsh store to r9", "VMOVSH",
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[]ExtOperand{ExtXmm(30), ExtMemory(9, 0)},
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"62457e081131", "62 45 7e 08 11 31 vmovsh %xmm30,(%r9)"},
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{"vmovsh store disp8", "VMOVSH",
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[]ExtOperand{ExtXmm(30), ExtMemory(1, 127)},
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"62657e0811717f", "62 65 7e 08 11 71 7f vmovsh %xmm30,0xfe(%rcx) (Disp8(7f))"},
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{"vmovsh store negative disp32", "VMOVSH",
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[]ExtOperand{ExtXmm(30), ExtMemory(13, -200)},
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"62457e0811b538ffffff", ""},
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{"vmovw load from r9", "VMOVW",
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[]ExtOperand{ExtMemory(9, 0), ExtXmm(30)},
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"62457d086e31", "62 45 7d 08 6e 31 vmovw (%r9),%xmm30"},
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{"vmovw load disp8", "VMOVW",
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[]ExtOperand{ExtMemory(1, 127), ExtXmm(30)},
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"62657d086e717f", "62 65 7d 08 6e 71 7f vmovw 0xfe(%rcx),%xmm30 (Disp8(7f))"},
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{"vmovw store to r9", "VMOVW",
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[]ExtOperand{ExtXmm(30), ExtMemory(9, 0)},
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"62457d087e31", "62 45 7d 08 7e 31 vmovw %xmm30,(%r9)"},
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{"vmovw store disp8", "VMOVW",
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[]ExtOperand{ExtXmm(30), ExtMemory(1, 127)},
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"62657d087e717f", "62 65 7d 08 7e 71 7f vmovw %xmm30,0xfe(%rcx) (Disp8(7f))"},
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{"vaddsh memory source", "VADDSH",
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[]ExtOperand{ExtXmm(29), ExtMemory(9, 0), ExtXmm(30)},
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"624516005831", "62 45 16 00 58 31 vaddsh (%r9),%xmm29,%xmm30"},
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{"vaddsh memory source disp8", "VADDSH",
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[]ExtOperand{ExtXmm(29), ExtMemory(1, 127), ExtXmm(30)},
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"6265160058717f", "62 65 16 00 58 71 7f vaddsh 0xfe(%rcx),%xmm29,%xmm30 (Disp8(7f))"},
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{"vaddsh memory source disp32", "VADDSH",
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[]ExtOperand{ExtXmm(29), ExtMemory(2, 8128), ExtXmm(30)},
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"6265160058b2c01f0000", ""},
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{"vsubsh memory source", "VSUBSH",
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[]ExtOperand{ExtXmm(29), ExtMemory(9, 0), ExtXmm(30)},
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"624516005c31", "62 45 16 00 5c 31 vsubsh (%r9),%xmm29,%xmm30"},
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{"vmulsh memory source disp8", "VMULSH",
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[]ExtOperand{ExtXmm(29), ExtMemory(1, 127), ExtXmm(30)},
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"6265160059717f", "62 65 16 00 59 71 7f vmulsh 0xfe(%rcx),%xmm29,%xmm30 (Disp8(7f))"},
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{"vdivsh memory source", "VDIVSH",
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[]ExtOperand{ExtXmm(29), ExtMemory(9, 0), ExtXmm(30)},
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"624516005e31", "62 45 16 00 5e 31 vdivsh (%r9),%xmm29,%xmm30"},
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{"vminsh memory source disp8", "VMINSH",
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[]ExtOperand{ExtXmm(29), ExtMemory(1, 127), ExtXmm(30)},
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"626516005d717f", "62 65 16 00 5d 71 7f vminsh 0xfe(%rcx),%xmm29,%xmm30 (Disp8(7f))"},
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{"vmaxsh memory source", "VMAXSH",
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[]ExtOperand{ExtXmm(29), ExtMemory(9, 0), ExtXmm(30)},
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"624516005f31", "62 45 16 00 5f 31 vmaxsh (%r9),%xmm29,%xmm30"},
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{"vsqrtsh memory source", "VSQRTSH",
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[]ExtOperand{ExtXmm(29), ExtMemory(9, 0), ExtXmm(30)},
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"624516005131", "62 45 16 00 51 31 vsqrtsh (%r9),%xmm29,%xmm30"},
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{"vsqrtsh memory source negative disp8", "VSQRTSH",
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[]ExtOperand{ExtXmm(29), ExtMemory(2, -128), ExtXmm(30)},
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"62651600517280", "62 65 16 87 51 72 80 vsqrtsh -0x100(%rdx),%xmm29,%xmm30 (Disp8(80); the GNU row adds {k7}{z})"},
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// High registers in a 512-bit form exercise the EVEX extension bits:
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// with both sources above 15 the B bar and X bar bits clear, while the
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// destination zmm23 keeps R bar set in byte one (derived from the
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@@ -386,6 +455,9 @@ func TestAmd64ExtTemplateIntegrity(t *testing.T) {
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if in.Form.Arity() < 2 || in.Form.Arity() > 4 {
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t.Errorf("%s: form %s carries an unusable arity %d", in.Name, in.Form, in.Form.Arity())
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}
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if in.Mem > in.Form.Arity() {
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t.Errorf("%s: Mem names operand %d, outside the form's %d positions", in.Name, in.Mem, in.Form.Arity())
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}
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}
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}
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@@ -466,6 +538,27 @@ func TestAmd64ExtRejects(t *testing.T) {
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{"mask beyond k7 on the compare", "VCMPSH",
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[]ExtOperand{ExtImmediate(7), ExtXmm(28), ExtXmm(29), ExtMask(8)},
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"outside 0-7"},
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{"memory in the arithmetic's first source", "VADDSH",
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[]ExtOperand{ExtMemory(9, 0), ExtXmm(28), ExtXmm(30)},
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"wants an XMM register"},
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{"memory in the arithmetic's destination", "VADDSH",
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[]ExtOperand{ExtXmm(28), ExtXmm(29), ExtMemory(9, 0)},
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"wants an XMM register"},
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{"memory where the general register belongs", "VCVTSI2SH",
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[]ExtOperand{ExtXmm(29), ExtMemory(9, 0), ExtXmm(30)},
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"wants a 32-bit general register"},
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{"memory as the compare's second source", "VCMPSH",
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[]ExtOperand{ExtImmediate(7), ExtXmm(28), ExtMemory(9, 0), ExtMask(5)},
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"wants an XMM register"},
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{"memory as the intersect source", "VP2INTERSECTD",
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[]ExtOperand{ExtZmm(2), ExtMemory(9, 0), ExtMask(0)},
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"wants a ZMM register"},
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{"memory as the convert's source", "VCVTSS2SH",
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[]ExtOperand{ExtXmm(28), ExtMemory(9, 0), ExtXmm(30)},
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"wants an XMM register"},
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{"memory as the control byte", "VGETMANTSH",
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[]ExtOperand{ExtMemory(9, 0), ExtXmm(28), ExtXmm(29), ExtXmm(30)},
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"wants an immediate control byte"},
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} {
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in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
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_, err := in.Encode(tt.ops)
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@@ -486,6 +579,50 @@ func TestAmd64ExtRejects(t *testing.T) {
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}
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}
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// TestAmd64ExtMemoryFormRejects covers the shapes the memory forms refuse:
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// a register in the load's memory position, a memory operand in the store's
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// register position, and the out-of-range bases and displacements. The
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// rows resolve against the load and store entries themselves, which the
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// name-and-class lookup cannot pick alone: the register forms of the same
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// mnemonics share the class.
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func TestAmd64ExtMemoryFormRejects(t *testing.T) {
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load := func(in ExtInstr) bool { return in.Form == ExtFormAmdMemVec }
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store := func(in ExtInstr) bool { return in.Form == ExtFormAmdVecMem }
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for _, tt := range []struct {
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name string
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mnem string
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pick func(ExtInstr) bool
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ops []ExtOperand
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quote string
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}{
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{"vector in the load's memory position", "VMOVSH", load,
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[]ExtOperand{ExtXmm(29), ExtXmm(30)},
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"wants a memory operand"},
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{"memory in the store's register position", "VMOVSH", store,
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[]ExtOperand{ExtMemory(9, 0), ExtMemory(1, 0)},
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"wants an XMM register"},
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{"vector in the store's memory position", "VMOVSH", store,
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[]ExtOperand{ExtXmm(29), ExtXmm(30)},
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"wants a memory operand"},
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{"base beyond r15 on the load", "VMOVW", load,
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[]ExtOperand{ExtMemory(16, 0), ExtXmm(30)},
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"outside 0-15"},
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{"displacement past the signed 32-bit range on the store", "VMOVW", store,
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[]ExtOperand{ExtXmm(30), ExtMemory(8, 1<<32)},
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"outside the signed 32-bit range"},
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} {
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in := amd64ExtInstr(t, tt.mnem, ExtXMM, tt.pick)
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_, err := in.Encode(tt.ops)
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if err == nil {
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t.Errorf("%s: encode succeeded, want an error", tt.name)
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continue
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}
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if !strings.Contains(err.Error(), tt.quote) {
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t.Errorf("%s: error %q lacks %q", tt.name, err, tt.quote)
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}
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}
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}
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// operandClass names the vector class a row exercises, the key the entry
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// lookup resolves with.
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func operandClass(t *testing.T, ops []ExtOperand) ExtOperandKind {
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@@ -554,7 +691,7 @@ func TestAmd64ExtArchBinding(t *testing.T) {
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t.Errorf("Extensions(%s) carries %d instructions, want none", a, len(got))
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}
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}
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if got := Extensions(AMD64); len(got) != 66 {
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t.Errorf("the amd64 layer registers %d instructions, want 66", len(got))
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if got := Extensions(AMD64); len(got) != 70 {
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t.Errorf("the amd64 layer registers %d instructions, want 70", len(got))
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}
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}
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