petrbalvin/gasm-sdk
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases 36 Wiki Activity

fix(arm64): store-exclusive operand order and large-frame parity

Browse Source 
Assisted-by: GLM 5.3
This commit is contained in:
petrbalvin
2026-09-20 00:38:24 +02:00
parent a6f3828c02
commit d315a998ce
6 changed files with 382 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files
testdata/verify/exclusive_arm64.s
Vendored
+81
View File
@@ -0,0 +1,81 @@
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause
// Exclusive load/store family, LSE atomics and their memory operands,
// byte-parity-checked against go tool asm. The toolchain parses the FIRST
// register of an exclusive store as the data register and the LAST as the
// status register, and takes register pairs as (Rt1, Rt2) operands.
#include "textflag.h"
TEXT ·loads(SB), NOSPLIT, $0-0
LDXR (R1), R2
LDXRB (R1), R3
LDXRH (R1), R4
LDXRW (R1), R5
LDAXR (R1), R2
LDAXRB (R1), R3
LDAXRH (R1), R4
LDAXRW (R1), R5
LDXR (RSP), R2
LDXRB (RSP), R3
LDXRH (RSP), R4
LDXRW (RSP), R5
LDAXR (RSP), R2
LDAXRB (RSP), R3
LDAXRH (RSP), R4
RET
TEXT ·stores(SB), NOSPLIT, $0-0
STXR R2, (R1), R6
STXRB R3, (R1), R6
STXRH R4, (R1), R6
STXRW R5, (R1), R6
STLXR R2, (R1), R6
STLXRB R3, (R1), R6
STLXRH R4, (R1), R6
STLXRW R5, (R1), R6
STXR R2, (RSP), R6
STXRB R3, (RSP), R6
STXRH R4, (RSP), R6
STXRW R5, (RSP), R6
STLXR R2, (RSP), R6
STLXRB R3, (RSP), R6
STLXRH R4, (RSP), R6
RET
TEXT ·pairs(SB), NOSPLIT, $0-0
LDXP (R1), (R2, R3)
LDXPW (R1), (R2, R3)
LDAXP (R1), (R2, R3)
LDAXPW (R1), (R2, R3)
STXP (R2, R3), (R1), R6
STXPW (R2, R3), (R1), R6
STLXP (R2, R3), (R1), R6
STLXPW (R2, R3), (R1), R6
LDXP (RSP), (R2, R3)
LDXPW (RSP), (R2, R3)
LDAXP (RSP), (R4, R5)
LDAXPW (RSP), (R4, R5)
STXP (R2, R3), (RSP), R6
STXPW (R2, R3), (RSP), R6
STLXP (R4, R5), (RSP), R7
RET
TEXT ·atomics(SB), NOSPLIT, $0-0
LDADDB R2, (R1), R3
LDADDH R2, (R1), R3
LDADDW R2, (R1), R3
LDADDD R2, (R1), R3
LDADDB R2, (R1), ZR
LDADDH R2, (R1), ZR
LDADDW R2, (R1), ZR
LDADDD R2, (R1), ZR
CASW R2, (R1), R3
CASD R2, (R1), R3
CASW R2, (R1), ZR
CASD R2, (R1), ZR
SWPW R2, (R1), R3
SWPD R2, (R1), R3
SWPD R2, (R1), ZR
RET