test(disasm): drop the closed byte-width divergences from the parity map

The operand-width reconciliation closes the byte-register fixture lines
byte for byte: XADDL, XCHGL, CMPXCHGL and CRC32 with byte registers, the
ALU and TEST immediates against AL and DL, and the unlisted accumulator
short forms.  MOVL $0x7, DL stays mapped for the legal-encoding choice
alone: the toolchain's own table says "c6c207 or b207", go tool asm emits
b207, and the fixed-point invariant holds with it.

Assisted-by: GLM 5.3

disasm/parity_test.go

@@ -200,26 +200,22 @@ var toolchainRenderNames = map[string]bool{
 // encoder, reported and not fixed here; the disassembler text itself is the
 // toolchain's.  amd64: CMOVLE encodes the CMOVE condition code; MOVQ to a
 // memory operand drops the FS segment prefix; MOVQ2DQ takes the F2 prefix
-// and lands in MOVDQ2Q; CRC32 with a 16-bit register widens to 32 bits.
-// arm64: the CRC32 forms take the wrong Rm; the register-indexed load and
-// store forms lose the index operand; BFXIL encodes as BFI with shifted
-// immediates.  loong64: the SC displacement encodes unscaled.
-// riscv64: FSGNJXS encodes as FMIN.S; FCLASSS and FCLASSD encode as MOVF;
-// the AUIPC immediate loses its high bits.  Keyed by the fixture text.
+// and lands in MOVDQ2Q; MOVD re-encodes through the 64-bit MOVQ alias; the
+// byte-register lines that render with the L suffix encode the byte form
+// since the operand-width reconciliation, MOVL $0x7, DL keeping only the
+// legal-encoding difference (the toolchain's own table says "c6c207 or
+// b207", and go tool asm emits b207, so the fixed-point invariant holds
+// where the pinned bytes took the alternative).  arm64: the CRC32 forms
+// take the wrong Rm; the register-indexed load and store forms lose the
+// index operand; BFXIL encodes as BFI with shifted immediates.  loong64:
+// the SC displacement encodes unscaled.  riscv64: FSGNJXS encodes as
+// FMIN.S; FCLASSS and FCLASSD encode as MOVF; the AUIPC immediate loses
+// its high bits.  Keyed by the fixture text.
 var encoderDivergences = map[string]bool{
 	"CMOVLE 0(BX), DX":             true,
 	"MOVQ FS:0, DX":                true,
 	"MOVQ2DQ M2, X11":              true,
-	"CRC32 DL, R11":                true,
-	"XADDL DL, DL":                 true,
-	"XCHGL DL, DL":                 true,
-	"CMPL AL, $0x7":                true,
-	"CMPXCHGL DL, DL":              true,
-	"ANDL $0x7, AL":                true,
-	"SBBL $0x7, DL":                true,
-	"SBBL DL, R11":                 true,
-	"SUBL $0x7, AL":                true,
-	"TESTL R11, DL":                true,
+	"MOVL $0x7, DL":                true,
 	"BFXIL $26, R8, $16, R20":      true,
 	"CRC32B R17, R8, R16":          true,
 	"CRC32CB R19, R27, R22":        true,
@@ -233,14 +229,9 @@ var encoderDivergences = map[string]bool{
 	"FCLASSS F0, X5":               true,
 	"FCLASSD F0, X5":               true,
 	"AUIPC $524287, X10":           true,
-	// From the unlisted amd64 fixture: the 8-bit accumulator and register
-	// immediate short forms render with a 32-bit suffix ("ADDL $0x7, AL"),
-	// which re-assembles as the 32-bit form; MOVD re-encodes as the 64-bit
-	// MOVQ form; POPW drops the operand-size prefix.  Findings for asm,
+	// From the unlisted amd64 fixture: MOVD re-encodes through the 64-bit
+	// MOVQ alias; POPW drops the operand-size prefix.  Findings for asm,
 	// reported and not fixed here.
-	"ADDL $0x7, AL": true,
-	"MOVL $0x7, DL": true,
-	"SBBL $0x7, AL": true,
 	"POPW FS":       true,
 	"POPW GS":       true,
 	"MOVD DX, M2":   true,