feat(asm): encode the arm64 Q-width FP load and store
FMOVQ routes through the MOV load/store machinery in the plain, post-index, pre-index and static-symbol forms. The Q width carries its size in the opc field, so the store spelling is opc=10 and the access scales by sixteen; both come from helpers now instead of the size exponent. The static-symbol form takes the toolchain's twelve-byte ADRP + ADD + access fallback with the R_ADDRARM64 pair. The register-to-register and immediate forms stay rejected, matching the toolchain's own table. Assisted-by: GLM 5.3 Flash
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@@ -228,11 +228,12 @@ func arm64PCAlignPad(pos int, instr *ast.Instr) int {
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}
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// isARM64MovMnemonic reports whether m is one of the MOV-family spellings the
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// arm64 encoder treats as the MOV pseudo-instruction.
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// arm64 encoder treats as the MOV pseudo-instruction. FMOVQ rides the same
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// load/store machinery but carries no register-move or immediate form.
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func isARM64MovMnemonic(m string) bool {
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switch m {
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case "MOV", "MOVD", "MOVW", "MOVWU", "MOVH", "MOVHU", "MOVB", "MOVBU",
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"FMOVS", "FMOVD":
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"FMOVS", "FMOVD", "FMOVQ":
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return true
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}
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return false
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@@ -279,7 +280,7 @@ func arm64InstrSize(instr *ast.Instr, fi arm64FrameInfo, pos int) int {
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}
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switch mnem {
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case "MOV", "MOVD", "MOVW", "MOVWU", "MOVH", "MOVHU", "MOVB", "MOVBU",
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"FMOVS", "FMOVD":
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"FMOVS", "FMOVD", "FMOVQ":
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return arm64MovSize(mnem, ops, fi)
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case "ADD", "ADDW", "SUB", "SUBW", "CMP", "CMPW", "CMN", "CMNW",
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"ADDS", "ADDSW", "SUBS", "SUBSW":
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@@ -354,7 +355,7 @@ func encodeARM64Instr(instr *ast.Instr, pc int, offsets map[string]int, fi arm64
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case "BL", "CALL":
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return encodeARM64Branch(mnem, ops, pc, offsets, true, relocs, resolve)
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case "MOV", "MOVD", "MOVW", "MOVWU", "MOVH", "MOVHU", "MOVB", "MOVBU",
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"FMOVS", "FMOVD":
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"FMOVS", "FMOVD", "FMOVQ":
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return encodeARM64Mov(instr, mnem, "", fi, relocs)
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}
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@@ -1479,6 +1480,20 @@ func encodeARM64Mov(instr *ast.Instr, mnem string, wb string, fi arm64FrameInfo,
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}
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src, dst := ops[0], ops[1]
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if mnem == "FMOVQ" {
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// The 128-bit FP move is a pure memory access in the toolchain: its
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// table carries no register-to-register or immediate row, and both
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// spellings are rejected ("illegal combination"), so only the
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// load/store and static-symbol forms exist here either.
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loadOK := arm64IsMemOperand(src) && !arm64IsMemOperand(dst) && !isImmOperand(src)
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storeOK := arm64IsMemOperand(dst) && !arm64IsMemOperand(src) && !isImmOperand(src)
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sbLoad := src.Addr.Sym != nil && src.Addr.Sym.Pseudo == "SB"
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sbStore := dst.Addr.Sym != nil && dst.Addr.Sym.Pseudo == "SB"
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if !loadOK && !storeOK && !sbLoad && !sbStore {
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return nil, fmt.Errorf("%s: only the memory load and store forms exist", mnem)
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}
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}
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if wb != "" {
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switch {
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case isMemOperand(src) && !isMemOperand(dst):
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@@ -1609,8 +1624,14 @@ func arm64MovSize(mnem string, ops []*ast.Operand, fi arm64FrameInfo) int {
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}
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return len(b)
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case src.Addr.Sym != nil && src.Addr.Sym.Pseudo == "SB":
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if mnem == "FMOVQ" {
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return 12 // ADRP + ADD + LDR: the unaligned-access fallback
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}
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return 8 // ADRP + LDR
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case dst.Addr.Sym != nil && dst.Addr.Sym.Pseudo == "SB":
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if mnem == "FMOVQ" {
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return 12 // ADRP + ADD + STR: the unaligned-access fallback
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}
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return 8 // ADRP + STR
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case isMemOperand(src) || isMemOperand(dst):
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mem := src
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@@ -1623,7 +1644,7 @@ func arm64MovSize(mnem string, ops []*ast.Operand, fi arm64FrameInfo) int {
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if !ok {
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lt = a64LoadTable["MOVD"] // the MOV pseudo is a 64-bit access
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}
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scale := int64(1) << uint(lt.size)
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scale := a64LSScale(lt)
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if off >= 0 && off%scale == 0 && off/scale < 4096 {
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return 4
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}
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@@ -1876,7 +1897,7 @@ func encodeARM64MemOp(mnem string, mem *ast.Operand, reg int, load bool, fi arm6
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lt = a64LoadTable["MOVD"]
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}
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scale := int64(1) << uint(lt.size)
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scale := a64LSScale(lt)
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storeOpc := a64StoreOpc(lt)
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var opc int
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if load {
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@@ -1963,12 +1984,27 @@ func encodeARM64SBAddr(sym *ast.Symbol, rd int, relocs *[]Reloc) []byte {
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// encodeARM64SBLoad emits ADRP R27, 0; LDR Rd, [R27, 0] with relocations,
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// matching the toolchain: the scratch register is REGTMP (R27) and the pair
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// carries R_ARM64_PCREL_LDST64.
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// carries R_ARM64_PCREL_LDST64. FMOVQ has no LDST relocation width, so it
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// takes the toolchain's unaligned-access fallback instead (asm7.go case 65):
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// ADRP R27, 0; ADD R27, R27, 0; LDR with the R_ADDRARM64 pair.
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func encodeARM64SBLoad(sym *ast.Symbol, rd int, mnem string, relocs *[]Reloc) ([]byte, error) {
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lt, ok := a64LoadTable[mnem]
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if !ok {
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lt = a64LoadTable["MOVD"]
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}
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if mnem == "FMOVQ" {
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if relocs != nil {
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*relocs = append(*relocs,
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Reloc{Off: 0, After: 0, Name: sym.Name, Kind: RelArm64Addr, Addend: sym.Offset},
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Reloc{Off: 4, After: 4, Name: sym.Name, Kind: RelArm64Addr, Addend: sym.Offset},
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)
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}
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return a64WordsLE(
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a64ADR(1, 0, 0, 27), // ADRP R27, 0
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a64AddSub(1, 0, 0, 0, 0, 27, 27), // ADD $0, R27, R27
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a64LSU(uint32(lt.size), uint32(lt.V), uint32(lt.opc), 0, 27, uint32(rd)), // LDR Rd, (R27)
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), nil
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}
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if relocs != nil {
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*relocs = append(*relocs,
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Reloc{Off: 0, After: 8, Name: sym.Name, Kind: RelArm64LDST64, Addend: sym.Offset},
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@@ -1981,13 +2017,28 @@ func encodeARM64SBLoad(sym *ast.Symbol, rd int, mnem string, relocs *[]Reloc) ([
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}
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// encodeARM64SBStore emits ADRP R27, 0; STR Rs, [R27, 0] with relocations,
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// matching the toolchain's R27 scratch and R_ARM64_PCREL_LDST64 pair.
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// matching the toolchain's R27 scratch and R_ARM64_PCREL_LDST64 pair. FMOVQ
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// takes the twelve-byte ADRP + ADD + STR fallback with the R_ADDRARM64 pair,
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// the store-side twin of the load above (asm7.go case 64).
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func encodeARM64SBStore(sym *ast.Symbol, rs int, mnem string, relocs *[]Reloc) ([]byte, error) {
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lt, ok := a64LoadTable[mnem]
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if !ok {
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lt = a64LoadTable["MOVD"]
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}
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storeOpc := a64StoreOpc(lt)
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if mnem == "FMOVQ" {
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if relocs != nil {
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*relocs = append(*relocs,
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Reloc{Off: 0, After: 0, Name: sym.Name, Kind: RelArm64Addr, Addend: sym.Offset},
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Reloc{Off: 4, After: 4, Name: sym.Name, Kind: RelArm64Addr, Addend: sym.Offset},
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)
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}
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return a64WordsLE(
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a64ADR(1, 0, 0, 27), // ADRP R27, 0
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a64AddSub(1, 0, 0, 0, 0, 27, 27), // ADD $0, R27, R27
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a64LSU(uint32(lt.size), uint32(lt.V), uint32(storeOpc), 0, 27, uint32(rs)), // STR Rs, (R27)
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), nil
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}
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if relocs != nil {
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*relocs = append(*relocs,
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Reloc{Off: 0, After: 8, Name: sym.Name, Kind: RelArm64LDST64, Addend: sym.Offset},
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