feat(asm): encode the arm64 Q-width FP load and store

FMOVQ routes through the MOV load/store machinery in the plain, post-index,
pre-index and static-symbol forms.  The Q width carries its size in the opc
field, so the store spelling is opc=10 and the access scales by sixteen;
both come from helpers now instead of the size exponent.  The static-symbol
form takes the toolchain's twelve-byte ADRP + ADD + access fallback with the
R_ADDRARM64 pair.  The register-to-register and immediate forms stay
rejected, matching the toolchain's own table.

Assisted-by: GLM 5.3 Flash
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petrbalvin committed 2026-10-07 02:36:24 +02:00
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commit daf7fad5b9
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@@ -679,6 +679,42 @@ func TestArm64AcquireRelease(t *testing.T) {
}
}
// TestArm64QMove pins the Q-width FP move against the toolchain words the
// corpus records: the plain, writeback and static-symbol load/store forms.
// FMOVQ carries no register-to-register or immediate form, and both are
// rejected the way the toolchain rejects them.
func TestArm64QMove(t *testing.T) {
got := arm64Words(t, "\tFMOVQ.P F13, 11(R10)\n\tFMOVQ.W F15, 11(R20)\n\tFMOVQ.P 11(R10), F13\n\tFMOVQ.W 11(R20), F15\n"+
"\tFMOVQ F0, 32(R5)\n\tFMOVQ F10, 65520(R10)\n\tFMOVQ 32(R5), F2\n")
want := []uint32{
0x3c80b54d, // FMOVQ.P F13, 11(R10)
0x3c80be8f, // FMOVQ.W F15, 11(R20)
0x3cc0b54d, // FMOVQ.P 11(R10), F13
0x3cc0be8f, // FMOVQ.W 11(R20), F15
0x3d8008a0, // FMOVQ F0, 32(R5)
0x3dbffd4a, // FMOVQ F10, 65520(R10)
0x3dc008a2, // FMOVQ 32(R5), F2
0xd65f03c0,
}
if len(got) != len(want) {
t.Fatalf("word count = %d, want %d", len(got), len(want))
}
for i := range want {
if got[i] != want[i] {
t.Errorf("word %d = %08x, want %08x", i, got[i], want[i])
}
}
for _, src := range []string{"\tFMOVQ F1, F2\n", "\tFMOVQ $1, R2\n", "\tFMOVQ $0, 8(R3)\n"} {
f, errs := parser.Parse("test_arm64.s", "#include \"textflag.h\"\n\nTEXT ·f(SB), NOSPLIT, $0-0\n"+src+"\tRET\n")
if len(errs) > 0 {
t.Fatalf("parse %q: %v", src, errs)
}
if _, err := AssembleFileARM64(f); err == nil {
t.Errorf("%q: assembled, want rejection", strings.TrimSpace(src))
}
}
}
// TestArm64BTI pins the landing-pad family against the toolchain words:
// only the uppercase C/J/JC spellings assemble, and bare BTI is a
// diagnostic, never a panic.