fix(disasm): name the amd64 families x/arch decodes to the zero opcode
x/arch reports the ADCX, ADOX, RDSEED, RDPID, TPAUSE, UMONITOR, UMWAIT and ENDBR families with no error but the degenerate zero instruction, which GoSyntax renders as Op(0) under its prefix decoration and with a length of one. A supplementary naming table keyed by the opcode pattern restores the toolchain's own spellings and lengths; the parity fixtures pin all 41 corpus rows (ENDBR32 alone, which the toolchain cannot spell, pins as bytes and text in the focused naming test). Assisted-by: GLM 5.3 Flash
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package disasm
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import (
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"testing"
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"sourcedock.dev/petrbalvin/gasm-sdk/arch"
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)
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// TestDegenerateNaming pins the supplementary naming table over the whole
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// set of encodings the Go toolchain's assembler corpus carries for the
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// families x/arch decodes to the degenerate zero instruction. Every row's
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// bytes are the corpus's own expected-encoding comments (machine-checked
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// by the toolchain's assembler test suite); every text is the corpus's own
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// spelling of the instruction.
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//
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// The rows whose text the encoder carries are also in
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// testdata/parity_amd64_unlisted.txt, where the parity and round-trip
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// tests pin them; this table covers them too so a fixture edit cannot
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// move one without this one noticing. ENDBR32 is the exception: the
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// toolchain knows no spelling for it (its obj/x86 table carries ENDBR64
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// only), so its text is pinned here as bytes and text, with no
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// round-trip.
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func TestDegenerateNaming(t *testing.T) {
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for _, tt := range []struct {
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code []byte
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text string
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}{
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// amd64enc.s: ADCXL (BX), DX // 660f38f613 and kin.
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{[]byte{0x66, 0x0f, 0x38, 0xf6, 0x13}, "ADCXL 0(BX), DX"},
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{[]byte{0x66, 0x41, 0x0f, 0x38, 0xf6, 0x13}, "ADCXL 0(R11), DX"},
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{[]byte{0x66, 0x0f, 0x38, 0xf6, 0xd2}, "ADCXL DX, DX"},
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{[]byte{0x66, 0x41, 0x0f, 0x38, 0xf6, 0xd3}, "ADCXL R11, DX"},
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{[]byte{0x66, 0x44, 0x0f, 0x38, 0xf6, 0x1b}, "ADCXL 0(BX), R11"},
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{[]byte{0x66, 0x45, 0x0f, 0x38, 0xf6, 0x1b}, "ADCXL 0(R11), R11"},
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{[]byte{0x66, 0x44, 0x0f, 0x38, 0xf6, 0xda}, "ADCXL DX, R11"},
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{[]byte{0x66, 0x45, 0x0f, 0x38, 0xf6, 0xdb}, "ADCXL R11, R11"},
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{[]byte{0x66, 0x48, 0x0f, 0x38, 0xf6, 0x13}, "ADCXQ 0(BX), DX"},
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{[]byte{0x66, 0x49, 0x0f, 0x38, 0xf6, 0x13}, "ADCXQ 0(R11), DX"},
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{[]byte{0x66, 0x48, 0x0f, 0x38, 0xf6, 0xd2}, "ADCXQ DX, DX"},
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{[]byte{0x66, 0x49, 0x0f, 0x38, 0xf6, 0xd3}, "ADCXQ R11, DX"},
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{[]byte{0x66, 0x4c, 0x0f, 0x38, 0xf6, 0x1b}, "ADCXQ 0(BX), R11"},
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{[]byte{0x66, 0x4d, 0x0f, 0x38, 0xf6, 0x1b}, "ADCXQ 0(R11), R11"},
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{[]byte{0x66, 0x4c, 0x0f, 0x38, 0xf6, 0xda}, "ADCXQ DX, R11"},
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{[]byte{0x66, 0x4d, 0x0f, 0x38, 0xf6, 0xdb}, "ADCXQ R11, R11"},
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// amd64enc.s: ADOXL (BX), DX // f30f38f613 and kin.
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{[]byte{0xf3, 0x0f, 0x38, 0xf6, 0x13}, "ADOXL 0(BX), DX"},
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{[]byte{0xf3, 0x41, 0x0f, 0x38, 0xf6, 0x13}, "ADOXL 0(R11), DX"},
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{[]byte{0xf3, 0x0f, 0x38, 0xf6, 0xd2}, "ADOXL DX, DX"},
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{[]byte{0xf3, 0x41, 0x0f, 0x38, 0xf6, 0xd3}, "ADOXL R11, DX"},
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{[]byte{0xf3, 0x44, 0x0f, 0x38, 0xf6, 0x1b}, "ADOXL 0(BX), R11"},
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{[]byte{0xf3, 0x45, 0x0f, 0x38, 0xf6, 0x1b}, "ADOXL 0(R11), R11"},
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{[]byte{0xf3, 0x44, 0x0f, 0x38, 0xf6, 0xda}, "ADOXL DX, R11"},
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{[]byte{0xf3, 0x45, 0x0f, 0x38, 0xf6, 0xdb}, "ADOXL R11, R11"},
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{[]byte{0xf3, 0x48, 0x0f, 0x38, 0xf6, 0x13}, "ADOXQ 0(BX), DX"},
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{[]byte{0xf3, 0x49, 0x0f, 0x38, 0xf6, 0x13}, "ADOXQ 0(R11), DX"},
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{[]byte{0xf3, 0x48, 0x0f, 0x38, 0xf6, 0xd2}, "ADOXQ DX, DX"},
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{[]byte{0xf3, 0x49, 0x0f, 0x38, 0xf6, 0xd3}, "ADOXQ R11, DX"},
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{[]byte{0xf3, 0x4c, 0x0f, 0x38, 0xf6, 0x1b}, "ADOXQ 0(BX), R11"},
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{[]byte{0xf3, 0x4d, 0x0f, 0x38, 0xf6, 0x1b}, "ADOXQ 0(R11), R11"},
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{[]byte{0xf3, 0x4c, 0x0f, 0x38, 0xf6, 0xda}, "ADOXQ DX, R11"},
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{[]byte{0xf3, 0x4d, 0x0f, 0x38, 0xf6, 0xdb}, "ADOXQ R11, R11"},
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// amd64enc.s: RDSEEDW DX // 660fc7fa.
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{[]byte{0x66, 0x0f, 0xc7, 0xfa}, "RDSEEDW DX"},
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{[]byte{0x66, 0x41, 0x0f, 0xc7, 0xfb}, "RDSEEDW R11"},
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// amd64enc_extra.s: RDPID DX // f30fc7fa.
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{[]byte{0xf3, 0x0f, 0xc7, 0xfa}, "RDPID DX"},
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{[]byte{0xf3, 0x41, 0x0f, 0xc7, 0xfb}, "RDPID R11"},
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// amd64enc_extra.s: TPAUSE BX // 660faef3 and kin.
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{[]byte{0x66, 0x0f, 0xae, 0xf3}, "TPAUSE BX"},
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{[]byte{0xf3, 0x0f, 0xae, 0xf3}, "UMONITOR BX"},
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{[]byte{0xf2, 0x0f, 0xae, 0xf3}, "UMWAIT BX"},
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// amd64enc_extra.s: ENDBR64 // f30f1efa; ENDBR32 has no
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// toolchain spelling.
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{[]byte{0xf3, 0x0f, 0x1e, 0xfa}, "ENDBR64"},
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{[]byte{0xf3, 0x0f, 0x1e, 0xfb}, "ENDBR32"},
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} {
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ins, err := Decode(arch.AMD64, tt.code, 0)
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if err != nil {
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t.Errorf("% x: %v", tt.code, err)
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continue
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}
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if ins.Text != tt.text || ins.Len != len(tt.code) {
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t.Errorf("% x: %q (%d bytes), want %q (%d)",
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tt.code, ins.Text, ins.Len, tt.text, len(tt.code))
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}
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}
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}
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// TestDegenerateNamingBoundaries guards the table's edges: bytes the
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// decoder rejects outright keep the placeholder, and the prefix
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// combinations no toolchain spelling carries stay unnamed even where the
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// decode is degenerate. The bare 0F 38 F6 form is the 32-bit ADCX of the
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// Intel manual; the toolchain's ADCXL spelling always carries the
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// operand-size override, so the bare form is left to the placeholder
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// rather than named to a spelling that would re-encode differently.
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func TestDegenerateNamingBoundaries(t *testing.T) {
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for _, tt := range []struct {
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code []byte
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text string
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}{
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// Rejected outright: RDSEED without the operand-size override
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// (the bare 0F C7 /7 register form), MONITORX and MWAITX, the
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// hint NOP CLDEMOTE.
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{[]byte{0x0f, 0xc7, 0xfa}, "???"},
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{[]byte{0x0f, 0x01, 0xfa}, "???"},
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{[]byte{0x0f, 0x01, 0xfb}, "???"},
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{[]byte{0x0f, 0x1c, 0x03}, "???"},
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// Degenerate but outside the table's prefix gates: repne ADCX is
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// no instruction the corpus names.
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{[]byte{0xf2, 0x0f, 0x38, 0xf6, 0xd2}, "REPNE; Op(0)"},
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// MONITOR and MWAIT decode as named opcodes and never reach the
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// table.
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{[]byte{0x0f, 0x01, 0xc8}, "MONITOR"},
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{[]byte{0x0f, 0x01, 0xc9}, "MWAIT"},
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} {
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ins, err := Decode(arch.AMD64, tt.code, 0)
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if err != nil {
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t.Errorf("% x: %v", tt.code, err)
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continue
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}
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if ins.Text != tt.text {
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t.Errorf("% x: %q, want %q", tt.code, ins.Text, tt.text)
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}
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}
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}
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