petrbalvin/gasm-sdk
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases 36 Wiki Activity

feat(riscv64,loong64): encode AMO atomics, vector slices and bit ops

Browse Source 
Assisted-by: GLM 5.3 Flash
This commit is contained in:
petrbalvin
2026-09-20 06:44:51 +02:00
parent ca3fdce0e0
commit de5d9f358e
12 changed files with 2059 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files
testdata/verify/atomics_loong64.s
Vendored
+49
View File
@@ -0,0 +1,49 @@
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause
// Differential kernel for the loong64 atomics: the AM* family in its plain
// and _dbar (acquire/release) forms, spelled as the runtime's
// atomic_loong64.s spells them. Every AM* takes three operands:
// value, (address), result.
#include "textflag.h"
TEXT ·plain(SB), NOSPLIT, $0-0
AMSWAPB R14, (R13), R12
AMSWAPH R14, (R13), R12
AMSWAPW R5, (R4), R6
AMSWAPV R5, (R4), R0
AMCASB R14, (R13), R12
AMCASH R6, (R4), R5
AMCASW R6, (R4), R5
AMCASV R6, (R4), R5
AMADDW R5, (R4), R0
AMADDV R14, (R13), R12
AMANDW R5, (R4), R6
AMANDV R5, (R4), R6
AMORW R5, (R4), R0
AMORV R5, (R4), R6
AMXORW R5, (R4), R6
AMXORV R5, (R4), R6
AMMAXW R5, (R4), R6
AMMAXV R5, (R4), R6
AMMINW R5, (R4), R6
AMMINV R5, (R4), R6
AMMAXWU R5, (R4), R6
AMMAXVU R5, (R4), R6
AMMINWU R5, (R4), R6
AMMINVU R5, (R4), R6
RET
TEXT ·dbar(SB), NOSPLIT, $0-0
AMADDDBW R5, (R4), R6
AMADDDBV R5, (R4), R6
AMANDDBW R5, (R6), R0
AMANDDBV R5, (R4), R6
AMORDBW R5, (R6), R0
AMORDBV R5, (R4), R6
AMSWAPDBW R5, (R4), R6
AMSWAPDBV R5, (R4), R0
AMCASDBW R6, (R4), R5
AMCASDBV R6, (R4), R5
RET
testdata/verify/atomics_riscv64.s
Vendored
+35
View File
@@ -0,0 +1,35 @@
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause
// Differential kernel for the riscv64 atomics: the RV64A AMO family and the
// load-reserved / store-conditional pair, in the toolchain's spelling
// (value, (address), result). Both orderings sit in the encodings: the
// table gives every AMO aq and rl, LR acquire and SC release.
#include "textflag.h"
TEXT ·amo(SB), NOSPLIT, $0-0
AMOSWAPW X5, (X6), X7
AMOSWAPD X5, (X6), X7
AMOADDW X5, (X6), X7
AMOADDD X5, (X6), X7
AMOANDW X5, (X6), X7
AMOANDD X5, (X6), X7
AMOORW X5, (X6), X7
AMOORD X5, (X6), X7
AMOXORW X5, (X6), X7
AMOXORD X5, (X6), X7
AMOMAXW X5, (X6), X7
AMOMAXD X5, (X6), X7
AMOMAXUW X5, (X6), X7
AMOMAXUD X5, (X6), X7
AMOMINUW X5, (X6), X7
AMOMINUD X5, (X6), X7
RET
TEXT ·lrsc(SB), NOSPLIT, $0-0
LRW (X5), X6
LRD (X5), X6
SCW X5, (X6), X7
SCD X5, (X6), X7
RET
testdata/verify/bitmanip_riscv64.s
Vendored
+64
View File
@@ -0,0 +1,64 @@
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause
// Differential kernel for the riscv64 toolchain-synthesised instructions:
// the Zbb-style pseudos the assembler expands instruction-for-instruction
// (ANDN/ORN, MIN/MAX, ROR and friends, the reversed branches, FABSD), the
// CSR read RDTIME and the FP sign-injection and fused-multiply-add forms.
#include "textflag.h"
TEXT ·logic(SB), NOSPLIT, $0-0
ANDN X19, X20, X21
ANDN X19, X20
ANDN X21, X19, X21
ORN X20, X19
ORN X20, X19, X21
MAX X26, X28, X29
MAX X26, X28
MAXU X28, X29, X30
MAXU X28, X29
MIN X29, X30, X5
MIN X29, X30
MINU X30, X5, X6
MINU X30, X5
MAX X5, X5
MAX X5, X5, X6
SEQZ X5, X6
NEG X5, X6
NEG X5
NOT X5
NOT X5, X6
NOP
RET
TEXT ·rotate(SB), NOSPLIT, $0-0
ROR X10, X11, X12
ROR X10, X11
ROR $63, X11
RORIW $31, X13, X14
RORIW $1, X14, X15
RORIW $3, X14
RORW X15, X16, X17
RORW $31, X13
RET
TEXT ·fp(SB), NOSPLIT, $0-0
FABSD F1, F2
FSGNJD F1, F0, F2
FMADDD F1, F2, F3, F4
FMSUBD F1, F2, F3, F4
FNMSUBD F1, F2, F3, F4
FMADDS F1, F2, F3, F4
FNMADDS F1, F2, F3, F4
RET
TEXT ·branches(SB), NOSPLIT, $0-0
BGT X5, X6, tgt
BLE X5, X6, tgt
BGTU X5, X6, tgt
BLEU X5, X6, tgt
tgt:
RDTIME X5
RET
testdata/verify/vector_loong64.s
Vendored
+85
View File
@@ -0,0 +1,85 @@
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause
// Differential kernel for the loong64 LSX/LASX slice: every function pairs
// with the same instructions in the go tool asm ground truth.
#include "textflag.h"
TEXT ·threeReg(SB), NOSPLIT, $0-0
VADDV V1, V2, V3
VADDW V1, V2, V3
VADDV V2, V1
VANDV V1, V2, V3
VANDV V1, V2
VXORV V1, V2, V3
VXORV V1, V2
VSEQB V1, V2, V3
VSEQV V1, V2, V3
VSRAB V1, V2, V3
VROTRW V1, V2, V3
VPCNTV V1, V2
XVADDV X1, X2, X3
XVADDV X2, X1
XVANDV X1, X2, X3
XVXORV X1, X2, X3
XVSEQB X1, X2, X3
XVSEQV X1, X2, X3
XVPCNTV X1, X2
RET
TEXT ·immediates(SB), NOSPLIT, $0-0
VANDB $0, V2, V3
VANDB $255, V2
VSEQB $3, V2, V3
VSEQV $15, V2, V3
VSRAB $0, V1, V2
VSRAB $7, V1, V2
VSRAB $6, V1
VROTRW $0, V1, V2
VROTRW $16, V1, V2
VROTRW $16, V1
XVANDB $1, X2, X2
RET
TEXT ·conditions(SB), NOSPLIT, $0-0
VSETNEV V1, FCC0
VSETANYEQB V1, FCC0
VSETANYEQV V2, FCC0
VSETALLNEV V0, FCC0
XVSETNEV X1, FCC0
XVSETANYEQB X1, FCC0
XVSETANYEQV X1, FCC0
XVSETALLNEV X1, FCC0
RET
TEXT ·fpConvert(SB), NOSPLIT, $0-0
FFINTDV F0, F1
FSEL FCC0, F3, F4, F3
FSEL FCC1, F1, F2
RET
TEXT ·memMoves(SB), NOSPLIT, $0-0
VMOVQ V1, V9
VMOVQ (R4), V2
VMOVQ 16(R4), V2
VMOVQ V0, (R4)
VMOVQ V0, 32(R4)
VMOVQ V0,-16(R6)
VMOVQ (R4)(R7), V3
VMOVQ V3, (R4)(R7)
XVMOVQ X3, X7
XVMOVQ (R4), X2
XVMOVQ X0, (R4)
XVMOVQ (R4)(R7), X4
XVMOVQ X0, (R4)(R7)
RET
TEXT ·elements(SB), NOSPLIT, $0-0
VMOVQ R6, V0.B16
VMOVQ R6, V12.W4
XVMOVQ R6, X0.B32
VMOVQ (R4), V4.W4
VMOVQ (R10), V0.W4
XVMOVQ (R4), X0.B32
RET
testdata/verify/vector_riscv64.s
Vendored
+53
View File
@@ -0,0 +1,53 @@
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause
// Differential kernel for the riscv64 RVV slice: the instructions GOROOT's
// vector kernels use (crypto/internal/fips140/subtle/xor_riscv64.s,
// internal/bytealg and internal/chacha8rand), spelled as they spell them.
#include "textflag.h"
TEXT ·config(SB), NOSPLIT, $0-0
VSETVLI X5, E8, M8, TA, MA, X6
VSETVLI X11, E8, M8, TA, MA, X5
VSETVLI X12, E8, M8, TA, MA, X5
VSETVLI X13, E8, M8, TU, MU, X15
VSETIVLI $4, E32, M1, TA, MA, X0
VSETIVLI $15, E32, M1, TA, MA, X12
VSETVLI $15, E32, M1, TA, MA, X12
VSETVLI X10, E16, M1, TU, MU, X12
VSETVLI X10, E32, M2, TA, MA, X12
VSETVLI X10, E64, M8, TU, MU, X12
VSETIVLI $31, E32, M1, TA, MA, X12
RET
TEXT ·loadsStores(SB), NOSPLIT, $0-0
VLE8V (X10), V8
VLE8V (X11), V16
VLE8V (X12), V16
VIDV V12
VMV4RV V8, V24
VSE8V V24, (X10)
VSE32V V0, (X11)
VSE32V V8, (X11)
VSE32V V15, (X11)
RET
TEXT ·segmented(SB), NOSPLIT, $0-0
VLSSEG4E32V (X14), X0, V0
VLSSEG8E32V (X10), X0, V4
RET
TEXT ·crypto(SB), NOSPLIT, $0-0
VADDVV V20, V4, V4
VADDVV V27, V11, V11
VADDVX X12, V12, V12
VXORVV V8, V16, V24
VXORVV V13, V13, V13
VMSEQVX X12, V8, V0
VMSNEVV V8, V16, V0
VFIRSTM V0, X6
VFIRSTM V0, X7
VSLLVI $8, V28, V30
VSRLVI $25, V29, V29
RET