feat(riscv64,loong64): encode AMO atomics, vector slices and bit ops

Assisted-by: GLM 5.3 Flash
2026-09-20 06:44:51 +02:00
parent ca3fdce0e0
commit de5d9f358e
12 changed files with 2059 additions and 37 deletions
@@ -0,0 +1,64 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+// Differential kernel for the riscv64 toolchain-synthesised instructions:
+// the Zbb-style pseudos the assembler expands instruction-for-instruction
+// (ANDN/ORN, MIN/MAX, ROR and friends, the reversed branches, FABSD), the
+// CSR read RDTIME and the FP sign-injection and fused-multiply-add forms.
+
+#include "textflag.h"
+
+TEXT ·logic(SB), NOSPLIT, $0-0
+	ANDN X19, X20, X21
+	ANDN X19, X20
+	ANDN X21, X19, X21
+	ORN  X20, X19
+	ORN  X20, X19, X21
+	MAX  X26, X28, X29
+	MAX  X26, X28
+	MAXU X28, X29, X30
+	MAXU X28, X29
+	MIN  X29, X30, X5
+	MIN  X29, X30
+	MINU X30, X5, X6
+	MINU X30, X5
+	MAX  X5, X5
+	MAX  X5, X5, X6
+	SEQZ X5, X6
+	NEG  X5, X6
+	NEG  X5
+	NOT  X5
+	NOT  X5, X6
+	NOP
+	RET
+
+TEXT ·rotate(SB), NOSPLIT, $0-0
+	ROR   X10, X11, X12
+	ROR   X10, X11
+	ROR   $63, X11
+	RORIW $31, X13, X14
+	RORIW $1, X14, X15
+	RORIW $3, X14
+	RORW  X15, X16, X17
+	RORW  $31, X13
+	RET
+
+TEXT ·fp(SB), NOSPLIT, $0-0
+	FABSD   F1, F2
+	FSGNJD  F1, F0, F2
+	FMADDD  F1, F2, F3, F4
+	FMSUBD  F1, F2, F3, F4
+	FNMSUBD F1, F2, F3, F4
+	FMADDS  F1, F2, F3, F4
+	FNMADDS F1, F2, F3, F4
+	RET
+
+TEXT ·branches(SB), NOSPLIT, $0-0
+	BGT    X5, X6, tgt
+	BLE    X5, X6, tgt
+	BGTU   X5, X6, tgt
+	BLEU   X5, X6, tgt
+
+tgt:
+	RDTIME X5
+	RET