feat(riscv64,loong64): encode AMO atomics, vector slices and bit ops

Assisted-by: GLM 5.3 Flash

testdata/verify/vector_riscv64.s

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+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+// Differential kernel for the riscv64 RVV slice: the instructions GOROOT's
+// vector kernels use (crypto/internal/fips140/subtle/xor_riscv64.s,
+// internal/bytealg and internal/chacha8rand), spelled as they spell them.
+
+#include "textflag.h"
+
+TEXT ·config(SB), NOSPLIT, $0-0
+	VSETVLI  X5, E8, M8, TA, MA, X6
+	VSETVLI  X11, E8, M8, TA, MA, X5
+	VSETVLI  X12, E8, M8, TA, MA, X5
+	VSETVLI  X13, E8, M8, TU, MU, X15
+	VSETIVLI $4, E32, M1, TA, MA, X0
+	VSETIVLI $15, E32, M1, TA, MA, X12
+	VSETVLI  $15, E32, M1, TA, MA, X12
+	VSETVLI  X10, E16, M1, TU, MU, X12
+	VSETVLI  X10, E32, M2, TA, MA, X12
+	VSETVLI  X10, E64, M8, TU, MU, X12
+	VSETIVLI $31, E32, M1, TA, MA, X12
+	RET
+
+TEXT ·loadsStores(SB), NOSPLIT, $0-0
+	VLE8V  (X10), V8
+	VLE8V  (X11), V16
+	VLE8V  (X12), V16
+	VIDV   V12
+	VMV4RV V8, V24
+	VSE8V  V24, (X10)
+	VSE32V V0, (X11)
+	VSE32V V8, (X11)
+	VSE32V V15, (X11)
+	RET
+
+TEXT ·segmented(SB), NOSPLIT, $0-0
+	VLSSEG4E32V (X14), X0, V0
+	VLSSEG8E32V (X10), X0, V4
+	RET
+
+TEXT ·crypto(SB), NOSPLIT, $0-0
+	VADDVV  V20, V4, V4
+	VADDVV  V27, V11, V11
+	VADDVX  X12, V12, V12
+	VXORVV  V8, V16, V24
+	VXORVV  V13, V13, V13
+	VMSEQVX X12, V8, V0
+	VMSNEVV V8, V16, V0
+	VFIRSTM V0, X6
+	VFIRSTM V0, X7
+	VSLLVI  $8, V28, V30
+	VSRLVI  $25, V29, V29
+	RET