feat(debug): multi-architecture debugger support for arm64, riscv64, loong64

Assisted-by: MiMo V2.5 Pro
2026-08-21 00:35:21 +02:00
parent 3acbdd6533
commit de9e211ff1
32 changed files with 2276 additions and 659 deletions
@@ -0,0 +1,85 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+//go:build linux && loong64
+
+package debug
+
+import "fmt"
+
+// SetReg modifies a register value in the debuggee.
+func (s *Session) SetReg(name string, value uint64) error {
+	regs, err := s.GetRegs()
+	if err != nil {
+		return err
+	}
+	switch name {
+	case "r0", "zero":
+		regs.R0 = value
+	case "r1", "ra":
+		regs.R1 = value
+	case "r2", "tp":
+		regs.R2 = value
+	case "r3", "sp":
+		regs.R3 = value
+	case "r4", "a0":
+		regs.R4 = value
+	case "r5", "a1":
+		regs.R5 = value
+	case "r6", "a2":
+		regs.R6 = value
+	case "r7", "a3":
+		regs.R7 = value
+	case "r8", "a4":
+		regs.R8 = value
+	case "r9", "a5":
+		regs.R9 = value
+	case "r10", "a6":
+		regs.R10 = value
+	case "r11", "a7":
+		regs.R11 = value
+	case "r12", "t0":
+		regs.R12 = value
+	case "r13", "t1":
+		regs.R13 = value
+	case "r14", "t2":
+		regs.R14 = value
+	case "r15", "t3":
+		regs.R15 = value
+	case "r16", "t4":
+		regs.R16 = value
+	case "r17", "t5":
+		regs.R17 = value
+	case "r18", "t6":
+		regs.R18 = value
+	case "r19", "t7":
+		regs.R19 = value
+	case "r20", "t8":
+		regs.R20 = value
+	case "r21", "fp":
+		regs.R21 = value
+	case "r22", "s0":
+		regs.R22 = value
+	case "r23", "s1":
+		regs.R23 = value
+	case "r24", "s2":
+		regs.R24 = value
+	case "r25", "s3":
+		regs.R25 = value
+	case "r26", "s4":
+		regs.R26 = value
+	case "r27", "s5":
+		regs.R27 = value
+	case "r28", "s6":
+		regs.R28 = value
+	case "r29", "s7":
+		regs.R29 = value
+	case "r30", "s8":
+		regs.R30 = value
+	case "r31", "pc":
+		regs.R31 = value
+	default:
+		return fmt.Errorf("debug: unknown register %q", name)
+	}
+	return s.SetRegs(&regs)
+}