diff --git a/arch/arm64_gen.go b/arch/arm64_gen.go
index 89108e7..10046fe 100644
--- a/arch/arm64_gen.go
+++ b/arch/arm64_gen.go
@@ -364,6 +364,8 @@ var arm64GeneratedInstrs = []string{
 	"REVW",
 	"ROR",
 	"RORW",
+	"RPRFM",
+	"SB",
 	"SBC",
 	"SBCS",
 	"SBCSW",
@@ -477,23 +479,68 @@ var arm64GeneratedInstrs = []string{
 	"UXTH",
 	"UXTHW",
 	"UXTW",
+	"VABS",
 	"VADD",
 	"VADDP",
 	"VADDV",
 	"VAND",
 	"VBCAX",
+	"VBIC",
 	"VBIF",
 	"VBIT",
 	"VBSL",
+	"VCLS",
+	"VCLZ",
 	"VCMEQ",
+	"VCMGE",
+	"VCMGT",
+	"VCMHI",
+	"VCMHS",
+	"VCMLE",
+	"VCMLT",
 	"VCMTST",
 	"VCNT",
 	"VDUP",
 	"VEOR",
 	"VEOR3",
 	"VEXT",
+	"VFABS",
+	"VFADD",
+	"VFADDP",
+	"VFCMEQ",
+	"VFCMGE",
+	"VFCMGT",
+	"VFCMLE",
+	"VFCMLT",
+	"VFCVTL",
+	"VFCVTL2",
+	"VFCVTN",
+	"VFCVTN2",
+	"VFCVTZS",
+	"VFCVTZU",
+	"VFDIV",
+	"VFMAX",
+	"VFMAXNM",
+	"VFMAXNMP",
+	"VFMAXNMV",
+	"VFMAXP",
+	"VFMAXV",
+	"VFMIN",
+	"VFMINNM",
+	"VFMINNMP",
+	"VFMINNMV",
+	"VFMINP",
+	"VFMINV",
 	"VFMLA",
 	"VFMLS",
+	"VFMUL",
+	"VFNEG",
+	"VFRINTM",
+	"VFRINTN",
+	"VFRINTP",
+	"VFRINTZ",
+	"VFSQRT",
+	"VFSUB",
 	"VLD1",
 	"VLD1R",
 	"VLD2",
@@ -502,11 +549,17 @@ var arm64GeneratedInstrs = []string{
 	"VLD3R",
 	"VLD4",
 	"VLD4R",
+	"VMLA",
+	"VMLS",
 	"VMOV",
 	"VMOVD",
 	"VMOVI",
 	"VMOVQ",
 	"VMOVS",
+	"VMUL",
+	"VNEG",
+	"VNOT",
+	"VORN",
 	"VORR",
 	"VPMULL",
 	"VPMULL2",
@@ -515,14 +568,47 @@ var arm64GeneratedInstrs = []string{
 	"VREV16",
 	"VREV32",
 	"VREV64",
+	"VSCVTF",
+	"VSHADD",
 	"VSHL",
+	"VSHRN",
+	"VSHRN2",
 	"VSLI",
+	"VSMAX",
+	"VSMAXP",
+	"VSMAXV",
+	"VSMIN",
+	"VSMINP",
+	"VSMINV",
+	"VSMLAL",
+	"VSMLAL2",
+	"VSMLSL",
+	"VSMLSL2",
+	"VSMULL",
+	"VSMULL2",
+	"VSQABS",
+	"VSQADD",
+	"VSQNEG",
+	"VSQSHL",
+	"VSQSUB",
+	"VSQXTN",
+	"VSQXTN2",
+	"VSQXTUN",
+	"VSQXTUN2",
+	"VSRHADD",
 	"VSRI",
+	"VSRSHR",
+	"VSSHL",
+	"VSSHLL",
+	"VSSHLL2",
+	"VSSHR",
 	"VST1",
 	"VST2",
 	"VST3",
 	"VST4",
 	"VSUB",
+	"VSXTL",
+	"VSXTL2",
 	"VTBL",
 	"VTBX",
 	"VTRN1",
@@ -530,8 +616,27 @@ var arm64GeneratedInstrs = []string{
 	"VUADDLV",
 	"VUADDW",
 	"VUADDW2",
+	"VUCVTF",
+	"VUHADD",
 	"VUMAX",
+	"VUMAXP",
+	"VUMAXV",
 	"VUMIN",
+	"VUMINP",
+	"VUMINV",
+	"VUMLAL",
+	"VUMLAL2",
+	"VUMLSL",
+	"VUMLSL2",
+	"VUMULL",
+	"VUMULL2",
+	"VUQADD",
+	"VUQSHL",
+	"VUQSUB",
+	"VUQXTN",
+	"VUQXTN2",
+	"VURHADD",
+	"VUSHL",
 	"VUSHLL",
 	"VUSHLL2",
 	"VUSHR",
@@ -541,6 +646,8 @@ var arm64GeneratedInstrs = []string{
 	"VUZP1",
 	"VUZP2",
 	"VXAR",
+	"VXTN",
+	"VXTN2",
 	"VZIP1",
 	"VZIP2",
 	"WFE",
diff --git a/arch/loong64_gen.go b/arch/loong64_gen.go
index 4aedc82..87f356e 100644
--- a/arch/loong64_gen.go
+++ b/arch/loong64_gen.go
@@ -152,6 +152,8 @@ var loong64GeneratedInstrs = []string{
 	"FNMADDF",
 	"FNMSUBD",
 	"FNMSUBF",
+	"FRINTD",
+	"FRINTF",
 	"FSCALEBD",
 	"FSCALEBF",
 	"FSEL",
@@ -177,7 +179,10 @@ var loong64GeneratedInstrs = []string{
 	"FTINTWF",
 	"JIRL",
 	"LL",
+	"LLACQV",
+	"LLACQW",
 	"LLV",
+	"LLW",
 	"LU12IW",
 	"LU32ID",
 	"LU52ID",
@@ -248,7 +253,11 @@ var loong64GeneratedInstrs = []string{
 	"ROTR",
 	"ROTRV",
 	"SC",
+	"SCQ",
+	"SCRELV",
+	"SCRELW",
 	"SCV",
+	"SCW",
 	"SGT",
 	"SGTU",
 	"SLL",
diff --git a/arch/riscv_gen.go b/arch/riscv_gen.go
index ff43613..b83d9e6 100644
--- a/arch/riscv_gen.go
+++ b/arch/riscv_gen.go
@@ -81,6 +81,9 @@ var riscvGeneratedInstrs = []string{
 	"CLD",
 	"CLDSP",
 	"CLI",
+	"CLMUL",
+	"CLMULH",
+	"CLMULR",
 	"CLUI",
 	"CLW",
 	"CLWSP",
@@ -95,13 +98,20 @@ var riscvGeneratedInstrs = []string{
 	"CSDSP",
 	"CSLLI",
 	"CSRAI",
+	"CSRC",
+	"CSRCI",
 	"CSRLI",
+	"CSRR",
 	"CSRRC",
 	"CSRRCI",
 	"CSRRS",
 	"CSRRSI",
 	"CSRRW",
 	"CSRRWI",
+	"CSRS",
+	"CSRSI",
+	"CSRW",
+	"CSRWI",
 	"CSUB",
 	"CSUBW",
 	"CSW",
@@ -259,6 +269,7 @@ var riscvGeneratedInstrs = []string{
 	"ORCB",
 	"ORI",
 	"ORN",
+	"PAUSE",
 	"RDCYCLE",
 	"RDINSTRET",
 	"RDTIME",
@@ -322,6 +333,8 @@ var riscvGeneratedInstrs = []string{
 	"VADDVI",
 	"VADDVV",
 	"VADDVX",
+	"VANDNVV",
+	"VANDNVX",
 	"VANDVI",
 	"VANDVV",
 	"VANDVX",
@@ -329,8 +342,17 @@ var riscvGeneratedInstrs = []string{
 	"VASUBUVX",
 	"VASUBVV",
 	"VASUBVX",
+	"VBREV8V",
+	"VBREVV",
+	"VCLMULHVV",
+	"VCLMULHVX",
+	"VCLMULVV",
+	"VCLMULVX",
+	"VCLZV",
 	"VCOMPRESSVM",
 	"VCPOPM",
+	"VCPOPV",
+	"VCTZV",
 	"VDIVUVV",
 	"VDIVUVX",
 	"VDIVVV",
@@ -743,10 +765,16 @@ var riscvGeneratedInstrs = []string{
 	"VREMUVX",
 	"VREMVV",
 	"VREMVX",
+	"VREV8V",
 	"VRGATHEREI16VV",
 	"VRGATHERVI",
 	"VRGATHERVV",
 	"VRGATHERVX",
+	"VROLVV",
+	"VROLVX",
+	"VRORVI",
+	"VRORVV",
+	"VRORVX",
 	"VRSUBVI",
 	"VRSUBVX",
 	"VS1RV",
@@ -950,6 +978,9 @@ var riscvGeneratedInstrs = []string{
 	"VWMULVX",
 	"VWREDSUMUVS",
 	"VWREDSUMVS",
+	"VWSLLVI",
+	"VWSLLVV",
+	"VWSLLVX",
 	"VWSUBUVV",
 	"VWSUBUVX",
 	"VWSUBUWV",