feat(arch): the shift-immediate tsz:imm3 scheme

Assisted-by: GLM 5.3 Flash

asm/extension_test.go

@@ -492,12 +492,36 @@ func TestExtensionNamesARM64(t *testing.T) {
 		"ZST1D",
 		"ZST1H",
 		"ZST1W",
+		// The shift-immediate classes: the narrowing and widening
+		// three-vector shifts and the predicated saturating left shifts,
+		// in first-occurrence order.
+		"ZSQSHRUNB",
+		"ZSQSHRUNT",
+		"ZSHRNB",
+		"ZSHRNT",
+		"ZRSHRNB",
+		"ZRSHRNT",
+		"ZSQSHRNB",
+		"ZSQSHRNT",
+		"ZSQRSHRNB",
+		"ZSQRSHRNT",
+		"ZUQSHRNB",
+		"ZUQSHRNT",
+		"ZUQRSHRNB",
+		"ZUQRSHRNT",
+		"ZSSHLLB",
+		"ZSSHLLT",
+		"ZUSHLLB",
+		"ZUSHLLT",
+		"ZSQSHL",
+		"ZSQSHLU",
+		"ZUQSHL",
 	}
 	got := ExtensionNames(arch.ARM64)
 	if strings.Join(got, ",") != strings.Join(want, ",") {
 		t.Errorf("ExtensionNames(ARM64) = %v, want %v", got, want)
 	}
-	if n := len(arch.Extensions(arch.ARM64)); n != 507 {
-		t.Errorf("the family registers %d instructions, want 507", n)
+	if n := len(arch.Extensions(arch.ARM64)); n != 528 {
+		t.Errorf("the family registers %d instructions, want 528", n)
 	}
 }