feat(riscv): add RISC-V RV64A, FP and CSR instruction support
Assisted-by: Kimi K3
This commit is contained in:
@@ -221,6 +221,63 @@ var riscvInstrTable = map[string]riscvEnc{
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"ECALL": {0x73, 0x0, 0x00},
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"EBREAK": {0x73, 0x0, 0x00},
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"FENCE": {0x0F, 0x0, 0x00},
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// RV64A — atomics (AMO opcode 0x2F).
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// funct3: 0x2 = word, 0x3 = doubleword. funct5 in bits [31:27].
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"AMOSWAPW": {0x2F, 0x2, 0x01 << 2},
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"AMOSWAPD": {0x2F, 0x3, 0x01 << 2},
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"AMOADDW": {0x2F, 0x2, 0x00 << 2},
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"AMOADDD": {0x2F, 0x3, 0x00 << 2},
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"AMOANDW": {0x2F, 0x2, 0x0C << 2},
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"AMOANDD": {0x2F, 0x3, 0x0C << 2},
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"AMOORW": {0x2F, 0x2, 0x06 << 2},
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"AMOORD": {0x2F, 0x3, 0x06 << 2},
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"AMOXORW": {0x2F, 0x2, 0x04 << 2},
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"AMOXORD": {0x2F, 0x3, 0x04 << 2},
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"AMOMAXW": {0x2F, 0x2, 0x14 << 2},
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"AMOMAXD": {0x2F, 0x3, 0x14 << 2},
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"AMOMINW": {0x2F, 0x2, 0x10 << 2},
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"AMOMIND": {0x2F, 0x3, 0x10 << 2},
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"AMOMAXUW": {0x2F, 0x2, 0x1C << 2},
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"AMOMAXUD": {0x2F, 0x3, 0x1C << 2},
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"AMOMINUW": {0x2F, 0x2, 0x18 << 2},
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"AMOMINUD": {0x2F, 0x3, 0x18 << 2},
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// RV64F/D — floating-point arithmetic.
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"FADDS": {0x53, 0x0, 0x00},
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"FSUBS": {0x53, 0x0, 0x04},
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"FMULS": {0x53, 0x0, 0x08},
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"FDIVS": {0x53, 0x0, 0x0C},
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"FADDD": {0x53, 0x0, 0x01},
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"FSUBD": {0x53, 0x0, 0x05},
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"FMULD": {0x53, 0x0, 0x09},
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"FDIVD": {0x53, 0x0, 0x0D},
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"FSQRTS": {0x53, 0x0, 0x2C},
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"FSQRTD": {0x53, 0x0, 0x2D},
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// FP loads/stores.
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"FLW": {0x07, 0x2, 0x00},
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"FLD": {0x07, 0x3, 0x00},
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"FSW": {0x27, 0x2, 0x00},
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"FSD": {0x27, 0x3, 0x00},
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// FP min/max.
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"FMINS": {0x53, 0x0, 0x14},
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"FMAXS": {0x53, 0x1, 0x14},
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"FMIND": {0x53, 0x0, 0x15},
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"FMAXD": {0x53, 0x1, 0x15},
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// RV64A — load-reserved / store-conditional (funct5 0x02 / 0x03).
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"LRW": {0x2F, 0x2, 0x02 << 2},
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"LRD": {0x2F, 0x3, 0x02 << 2},
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"SCW": {0x2F, 0x2, 0x03 << 2},
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"SCD": {0x2F, 0x3, 0x03 << 2},
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// FP compare — result in integer register (funct7 0x50/0x51).
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"FEQS": {0x53, 0x2, 0x50},
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"FLTS": {0x53, 0x1, 0x50},
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"FLES": {0x53, 0x0, 0x50},
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"FEQD": {0x53, 0x2, 0x51},
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"FLTD": {0x53, 0x1, 0x51},
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"FLED": {0x53, 0x0, 0x51},
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}
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// riscvRType encodes an R-type instruction: funct7 | rs2 | rs1 | funct3 | rd | opcode.
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@@ -229,6 +286,109 @@ func riscvRType(enc riscvEnc, rd, rs1, rs2 int) uint32 {
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(enc.funct3 << 12) | (uint32(rd) << 7) | enc.opcode
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}
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// riscvAMOType encodes an atomic (AMO) instruction.
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// Layout: funct5 | aq | rl | rs2 | rs1 | funct3 | rd | opcode.
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// The funct5 is stored in the upper bits of enc.funct7 (shifted left by 2).
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func riscvAMOType(enc riscvEnc, rd, rs1, rs2 int) uint32 {
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funct5 := enc.funct7 >> 2 // extract funct5 from the stored value
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return (funct5 << 27) | (uint32(rs2) << 20) | (uint32(rs1) << 15) |
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(enc.funct3 << 12) | (uint32(rd) << 7) | enc.opcode
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}
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// FP conversion instructions (FCVT, FMV). These use the rs2 field to
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// encode the conversion type rather than a register, so they are handled
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// separately from the general instruction table.
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type riscvCvtEnc struct {
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funct7 uint32 // bits [31:25]
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rs2 uint32 // conversion-type code in bits [24:20]
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opcode uint32 // always 0x53 (OP-FP)
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}
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var riscvCvtTable = map[string]riscvCvtEnc{
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// float → int (rs2 selects the integer width/sign).
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"FCVTWS": {0x60, 0x0, 0x53}, // float32 → int32
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"FCVTWUS": {0x60, 0x1, 0x53}, // float32 → uint32
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"FCVTLS": {0x60, 0x2, 0x53}, // float32 → int64
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"FCVTLUS": {0x60, 0x3, 0x53}, // float32 → uint64
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"FCVTWD": {0x61, 0x0, 0x53}, // float64 → int32
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"FCVTWUD": {0x61, 0x1, 0x53}, // float64 → uint32
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"FCVTLD": {0x61, 0x2, 0x53}, // float64 → int64
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"FCVTLUD": {0x61, 0x3, 0x53}, // float64 → uint64
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// int → float (rs2 selects the integer width/sign).
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"FCVTSW": {0x68, 0x0, 0x53}, // int32 → float32
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"FCVTSWU": {0x68, 0x1, 0x53}, // uint32 → float32
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"FCVTSL": {0x68, 0x2, 0x53}, // int64 → float32
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"FCVTSLU": {0x68, 0x3, 0x53}, // uint64 → float32
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"FCVTDW": {0x69, 0x0, 0x53}, // int32 → float64
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"FCVTDWU": {0x69, 0x1, 0x53}, // uint32 → float64
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"FCVTDL": {0x69, 0x2, 0x53}, // int64 → float64
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"FCVTDLU": {0x69, 0x3, 0x53}, // uint64 → float64
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// float → float width conversion.
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"FCVTSD": {0x20, 0x1, 0x53}, // float64 → float32
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"FCVTDS": {0x21, 0x0, 0x53}, // float32 → float64
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// Bit moves between integer and FP registers (no conversion).
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"FMVXD": {0x71, 0x0, 0x53}, // float64 → int64 (bit move)
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"FMVDX": {0x79, 0x0, 0x53}, // int64 → float64 (bit move)
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"FMVXW": {0x70, 0x0, 0x53}, // float32 → int32 (bit move)
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"FMVWX": {0x78, 0x0, 0x53}, // int32 → float32 (bit move)
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}
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// riscvCvtType encodes an FP conversion instruction.
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// Layout: funct7 | rs2(convtype) | rs1 | funct3(0) | rd | opcode.
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func riscvCvtType(enc riscvCvtEnc, rd, rs1 int) uint32 {
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return (enc.funct7 << 25) | (enc.rs2 << 20) | (uint32(rs1) << 15) |
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(uint32(rd) << 7) | enc.opcode
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}
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// R4-type fused multiply-add instructions (FMADD/FMSUB/FNMSUB/FNMADD).
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// These take 4 register operands: rs1, rs2, rs3, rd.
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// Layout: rs3 | fmt | rs2 | rs1 | rm | rd | opcode.
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type riscvFmaEnc struct {
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fmt uint32 // bits [26:25]: 0x0 = single, 0x1 = double
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opcode uint32 // bits [6:0]
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}
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var riscvFmaTable = map[string]riscvFmaEnc{
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"FMADDS": {0x0, 0x43}, // rd = rs1*rs2 + rs3
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"FMADDD": {0x1, 0x43},
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"FMSUBS": {0x0, 0x47}, // rd = rs1*rs2 - rs3
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"FMSUBD": {0x1, 0x47},
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"FNMSUBS": {0x0, 0x4B}, // rd = -(rs1*rs2) + rs3
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"FNMSUBD": {0x1, 0x4B},
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"FNMADDS": {0x0, 0x4F}, // rd = -(rs1*rs2) - rs3
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"FNMADDD": {0x1, 0x4F},
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}
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// riscvFmaType encodes an R4-type fused multiply-add instruction.
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func riscvFmaType(enc riscvFmaEnc, rd, rs1, rs2, rs3 int) uint32 {
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return (uint32(rs3) << 27) | (enc.fmt << 25) | (uint32(rs2) << 20) |
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(uint32(rs1) << 15) | (0x0 << 12) /* rm=dynamic */ | (uint32(rd) << 7) | enc.opcode
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}
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// CSR (Control and Status Register) instructions.
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// Format: csr[11:0] | rs1/zimm | funct3 | rd | opcode (0x73).
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type riscvCsrEnc struct {
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funct3 uint32 // bits [14:12]
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imm bool // true for CSRRWI/CSRRSI/CSRRCI (5-bit uimm variant)
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}
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var riscvCsrTable = map[string]riscvCsrEnc{
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"CSRRW": {0x1, false}, // rd=CSR, CSR=rs1
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"CSRRS": {0x2, false}, // rd=CSR, CSR |= rs1
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"CSRRC": {0x3, false}, // rd=CSR, CSR &= ~rs1
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"CSRRWI": {0x5, true}, // rd=CSR, CSR=uimm
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"CSRRSI": {0x6, true}, // rd=CSR, CSR |= uimm
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"CSRRCI": {0x7, true}, // rd=CSR, CSR &= ~uimm
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}
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// riscvCsrType encodes a CSR instruction.
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// csr is the 12-bit CSR address; src is either a register number or a 5-bit
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// unsigned immediate (depending on enc.imm).
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func riscvCsrType(enc riscvCsrEnc, rd, src int, csr int32) uint32 {
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return (uint32(csr&0xFFF) << 20) | (uint32(src&0x1F) << 15) |
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(enc.funct3 << 12) | (uint32(rd) << 7) | 0x73
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}
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// riscvIType encodes an I-type instruction: imm[11:0] | rs1 | funct3 | rd | opcode.
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func riscvIType(enc riscvEnc, rd, rs1 int, imm int32) uint32 {
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return (uint32(imm&0xFFF) << 20) | (uint32(rs1) << 15) |
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