feat(riscv): add RISC-V RV64A, FP and CSR instruction support

Assisted-by: Kimi K3
2026-08-02 11:45:00 +02:00
parent 801fb963c9
commit eee7a6d4a4
6 changed files with 455 additions and 0 deletions
@@ -0,0 +1,20 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+#include "textflag.h"
+
+// func atomicAdd(ptr *int64, val int64) int64
+TEXT ·atomicAdd(SB), NOSPLIT, $0-24
+	LD a+0(FP), A0
+	LD b+8(FP), A1
+	AMOADDD A1, (A0), A2
+	SD A2, ret+16(FP)
+	RET
+
+// func fpAdd(a, b float64) float64
+TEXT ·fpAdd(SB), NOSPLIT, $0-24
+	FLD a+0(FP), FA0
+	FLD b+8(FP), FA1
+	FADDD FA0, FA1, FA2
+	FSD FA2, ret+16(FP)
+	RET