feat(riscv): add RISC-V RV64A, FP and CSR instruction support

Assisted-by: Kimi K3
2026-08-02 11:45:00 +02:00
parent 801fb963c9
commit eee7a6d4a4
6 changed files with 455 additions and 0 deletions
@@ -0,0 +1,27 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+#include "textflag.h"
+
+// func readCSR(csr int64) int64
+// Reads a CSR into the return value.
+TEXT ·readCSR(SB), NOSPLIT, $0-16
+	LD a+0(FP), A0
+	CSRRS $0x300, X0, A1
+	SD A1, ret+8(FP)
+	RET
+
+// func setCSRBit(csr, bit int64) int64
+TEXT ·setCSRBit(SB), NOSPLIT, $0-24
+	LD a+0(FP), A0
+	LD b+8(FP), A1
+	CSRRS $0x304, A1, A2
+	SD A2, ret+16(FP)
+	RET
+
+// func writeCSR(val int64) int64
+TEXT ·writeCSR(SB), NOSPLIT, $0-16
+	LD a+0(FP), A0
+	CSRRW $0x305, A0, A1
+	SD A1, ret+8(FP)
+	RET