feat(riscv): add RISC-V RV64A, FP and CSR instruction support

Assisted-by: Kimi K3
2026-08-02 11:45:00 +02:00
parent 801fb963c9
commit eee7a6d4a4
6 changed files with 455 additions and 0 deletions
@@ -0,0 +1,24 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+#include "textflag.h"
+
+// func fma(a, b, c float64) float64
+// Computes a*b + c using fused multiply-add.
+TEXT ·fma(SB), NOSPLIT, $0-32
+	FLD a+0(FP), FA0
+	FLD b+8(FP), FA1
+	FLD c+16(FP), FA2
+	FMADDD FA0, FA1, FA2, FA3
+	FSD FA3, ret+24(FP)
+	RET
+
+// func fms(a, b, c float64) float64
+// Computes a*b - c using fused multiply-subtract.
+TEXT ·fms(SB), NOSPLIT, $0-32
+	FLD a+0(FP), FA0
+	FLD b+8(FP), FA1
+	FLD c+16(FP), FA2
+	FMSUBD FA0, FA1, FA2, FA3
+	FSD FA3, ret+24(FP)
+	RET