fix(asm): complete RISC-V compressed loads/stores and word arithmetic

Assisted-by: DeepSeek V4 Pro

CHANGELOG.md

@@ -55,6 +55,12 @@ Unreleased changes on the `development` branch.
   completed for `C.ADDI16SP`, `C.SLLI`, `C.SRLI`, `C.SRAI`, `C.ANDI`,
   `C.NOP`, `C.EBREAK`, `C.MV` (from `ADDI`/`ADD`) and the commutative
   `AND`/`OR`/`XOR` forms; the byte-exact ground-truth test now covers these.
+- **RISC-V compressed loads/stores and word arithmetic.**  RVC compression
+  now also covers the register-relative `C.LW`/`C.SW`/`C.LD`/`C.SD`/
+  `C.FLD`/`C.FSD` forms (in addition to the stack-relative `C.LWSP`/`C.SWSP`/
+  `C.LDSP`/`C.SDSP`), plus `C.ADDI4SPN`, `C.ADDW` and `C.SUBW`.  The
+  byte-exact ground-truth test exercises these against `GOARCH=riscv64
+  go tool asm`.
 - **Debugger watchpoint slots.**  `gasm debug`'s `watch` command always used
   hardware watchpoint slot 0, so a second `watch` call silently overwrote
   the first.  Watchpoint slots are now tracked in the `Session` (DR0–DR3);