feat(asm): emit the riscv64 local-exec TLS sequence
Assisted-by: GLM 5.3
This commit is contained in:
1 parent
f8dbd4f017
commit
f2892e4f59
6 files changed
+114
-29
No files matched your search
@@ -24,6 +24,8 @@ const (
|
||||
rRISCVPCRELHI20 = 23 // R_RISCV_PCREL_HI20
|
||||
rRISCVPCRELLO12I = 24 // R_RISCV_PCREL_LO12_I
|
||||
rRISCVPCRELLO12S = 25 // R_RISCV_PCREL_LO12_S
|
||||
rRISCVTPRELHI20 = 29 // R_RISCV_TPREL_HI20
|
||||
rRISCVTPRELLO12I = 30 // R_RISCV_TPREL_LO12_I
|
||||
// R_RISCV_32 (debug/elf 1): the absolute 32-bit address of a symbol,
|
||||
// the R_ADDR shape a 4-byte DATA field carries. R_RISCV_64 (2) lives
|
||||
// with the DWARF fixup constants as rRISCVAbs64.
|
||||
@@ -128,6 +130,15 @@ func (img *Image) ELFRISCVObject() ([]byte, error) {
|
||||
)
|
||||
case RelRISCVJal:
|
||||
relas = append(relas, elfRela{off: uint64(fn.Offset + r.Off), typ: rRISCVJAL, sym: idx, addend: r.Addend})
|
||||
case RelRISCVTLSLE:
|
||||
// The local-exec pair splits into the TPREL HI20 on the LUI
|
||||
// and the TPREL LO12_I on the ADDIW, both against the symbol
|
||||
// (a thread offset, not PC-relative, so the LO12 needs no
|
||||
// label indirection).
|
||||
relas = append(relas,
|
||||
elfRela{off: uint64(fn.Offset + r.Off), typ: rRISCVTPRELHI20, sym: idx, addend: r.Addend},
|
||||
elfRela{off: uint64(fn.Offset + r.Off + 4), typ: rRISCVTPRELLO12I, sym: idx, addend: r.Addend},
|
||||
)
|
||||
default:
|
||||
return nil, fmt.Errorf("relocation kind %v unsupported in ELF emission", r.Kind)
|
||||
}
|
||||
|
||||
Reference in new issue
Block a user