feat(riscv64): GOROOT instruction shapes, DATA order and offset expressions

Assisted-by: GLM 5.3 Flash

testdata/verify/misc_riscv64.s

@@ -0,0 +1,36 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+// GOROOT-derived shapes: the MOV width suffixes for narrow loads and the
+// branch-zero pseudos.  Deliberately absent: the immediate ALU aliases
+// (AND/SUB $imm) and the FP memory forms, whose RVC compression the encoder
+// does not reproduce yet, so a parity kernel could not hold them.
+
+#include "textflag.h"
+
+// func mix(x int64, y int64) int64
+TEXT ·mix(SB), NOSPLIT, $0-24
+	MOV	x+0(FP), X5
+	MOVWU	0(X5), X11
+	MOVB	1(X5), X12
+	MOVBU	2(X5), X13
+	ADD	X11, X12, X14
+	ADD	X13, X14, X15
+	MOV	X15, ret+16(FP)
+	RET
+
+// func branchy(n int64) int64
+TEXT ·branchy(SB), NOSPLIT, $0-16
+	MOV	n+0(FP), X5
+	BEQZ	X5, zero
+	BNEZ	X5, one
+	BLTZ	X5, zero
+	BGEZ	X5, one
+zero:
+	MOV	$0, X6
+	MOV	X6, ret+8(FP)
+	RET
+one:
+	MOV	$1, X6
+	MOV	X6, ret+8(FP)
+	RET