feat(asm): add RISC-V ELF relocatable object emission and SB relocation

support

asm/riscv_encode.go

@@ -228,6 +228,8 @@ var riscvInstrTable = map[string]riscvEnc{
 	"ECALL":  {0x73, 0x0, 0x00},
 	"EBREAK": {0x73, 0x0, 0x00},
 	"FENCE":  {0x0F, 0x0, 0x00},
+	// JALR — indirect jump/call (I-type).
+	"JALR": {0x67, 0x0, 0x00},
 
 	// RV64A — atomics (AMO opcode 0x2F).
 	// funct3: 0x2 = word, 0x3 = doubleword. funct5 in bits [31:27].
@@ -453,10 +455,35 @@ func rvcCR(funct4, rd, rs2 uint32) uint16 {
 }
 
 // rvcCI encodes a CI-type (immediate) compressed instruction.
+// Used for C.ADDI, C.LI, C.LUI, C.ADDIW — linear 6-bit immediate.
 func rvcCI(funct3, rd uint32, imm uint32) uint16 {
 	return uint16((funct3 << 13) | ((imm>>5)&1)<<12 | (rd << 7) | (imm&0x1F)<<2 | 0x2)
 }
 
+// rvcLSP encodes a CI-type stack-relative load: C.LDSP (funct3=3) or
+// C.FLDSP (funct3=1).  offset is the full byte offset; the immediate bits
+// are interleaved per the RISC-V spec: [5:3|8:6].
+func rvcLSP(funct3, rd uint32, offset uint32) uint16 {
+	// Bit interleave offset bits [5,4,3,8,7,6] → packed value.
+	packed := uint32(0)
+	for i, b := range []int{5, 4, 3, 8, 7, 6} {
+		packed |= ((offset >> b) & 1) << (5 - i)
+	}
+	return uint16((funct3 << 13) | ((packed>>5)&1)<<12 | (rd << 7) | (packed&0x1F)<<2 | 0x2)
+}
+
+// rvcSSP encodes a CSS-type stack-relative store: C.SDSP (funct3=7) or
+// C.FSDSP (funct3=5).  offset is the full byte offset; the immediate bits
+// are interleaved per the RISC-V spec: [5:3|8:6].
+func rvcSSP(funct3, rs2 uint32, offset uint32) uint16 {
+	// Bit interleave offset bits [5,4,3,8,7,6] → packed value.
+	packed := uint32(0)
+	for i, b := range []int{5, 4, 3, 8, 7, 6} {
+		packed |= ((offset >> b) & 1) << (5 - i)
+	}
+	return uint16((funct3 << 13) | (packed << 7) | (rs2 << 2) | 0x2)
+}
+
 // rvcCSS encodes a CSS-type (stack store) compressed instruction.
 func rvcCSS(funct3, rs2 uint32, imm uint32) uint16 {
 	return uint16((funct3 << 13) | (imm << 7) | (rs2 << 2) | 0x2)