feat(asm): encode the amd64 system, string and segment families
The no-operand flag and system controls, the sign-extension pair, the string primitives, the multi-byte no-ops, the cache controls, MOVBE, the compare-exchange doubles, the random source and FS/GS base pairs, the descriptor-table accesses, the 0F 00/01 register controls and the LAR/LSL selector reads and far-segment loads, each pinned byte for byte against go tool asm through every corpus line the toolchain's own amd64enc.s carries for the families (279 lines). Assisted-by: GLM 5.3 Flash
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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import "fmt"
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// This file implements the system, flag, string and segment families the Go
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// assembler carries: the no-operand controls, the string primitives, the
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// sign-extension pair, the multi-byte no-ops, the cache controls, MOVBE, the
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// compare-exchange doubles, the random source pair, the FS/GS base pair, the
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// descriptor-table controls and the LAR/LSL selector reads. Every encoding
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// here is pinned byte for byte against go tool asm through the corpus lines
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// in amd64_system_test.go.
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// systemNoOperand maps a fixed no-operand mnemonic to its opcode bytes, the
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// prefixes spelled out in full.
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var systemNoOperand = map[string][]byte{
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"CLC": {0xF8},
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"STC": {0xF9},
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"CMC": {0xF5},
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"CLI": {0xFA},
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"STI": {0xFB},
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"HLT": {0xF4},
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"ICEBP": {0xF1},
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"XLAT": {0xD7},
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"LAHF": {0x9F},
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"SAHF": {0x9E},
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"PUSHFW": {0x66, 0x9C},
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"POPFW": {0x66, 0x9D},
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"IRETW": {0x66, 0xCF},
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"IRETL": {0xCF},
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"IRETQ": {0x48, 0xCF},
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"UD1": {0x0F, 0xB9},
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"UD2": {0x0F, 0x0B},
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"CLAC": {0x0F, 0x01, 0xCA},
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"STAC": {0x0F, 0x01, 0xCB},
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"CLTS": {0x0F, 0x06},
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"INVD": {0x0F, 0x08},
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"WBINVD": {0x0F, 0x09},
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"SWAPGS": {0x0F, 0x01, 0xF8},
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"RSM": {0x0F, 0xAA},
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"MONITOR": {0x0F, 0x01, 0xC8},
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"MWAIT": {0x0F, 0x01, 0xC9},
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"RDMSR": {0x0F, 0x32},
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"WRMSR": {0x0F, 0x30},
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"RDPMC": {0x0F, 0x33},
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"RDPKRU": {0x0F, 0x01, 0xEE},
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"WRPKRU": {0x0F, 0x01, 0xEF},
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"XSETBV": {0x0F, 0x01, 0xD1},
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"SYSENTER": {0x0F, 0x34},
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"SYSENTER64": {0x48, 0x0F, 0x34},
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"SYSEXIT": {0x0F, 0x35},
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"SYSEXIT64": {0x48, 0x0F, 0x35},
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"SYSRET": {0x0F, 0x07},
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"CBW": {0x66, 0x98},
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"CWDE": {0x98},
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"CDQE": {0x48, 0x98},
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"CWD": {0x66, 0x99},
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"CDQ": {0x99},
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"CQO": {0x48, 0x99},
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}
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// stringOp maps the string-primitive bases to their 32-bit opcode; the byte
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// form is one lower, the word spelling carries 0x66 and the quad spelling
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// REX.W, exactly the prefix ladder newInstr applies.
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var stringOp = map[string]byte{
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"CMPS": 0xA7,
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"INS": 0x6D,
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"LODS": 0xAD,
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"OUTS": 0x6F,
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"SCAS": 0xAF,
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}
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// nopWidth maps the multi-byte no-op spellings to their operand size.
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var nopWidth = map[string]int{
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"NOPW": 2,
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"NOPL": 4,
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"NOPQ": 8,
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}
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// cacheControl maps the one-memory-operand cache controls to their mandatory
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// prefix, opcode group and /digit.
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var cacheControl = map[string]struct {
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prefix byte
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op []byte
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digit int
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}{
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"CLFLUSH": {0, []byte{0x0F, 0xAE}, 7},
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"CLFLUSHOPT": {0x66, []byte{0x0F, 0xAE}, 7},
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"INVLPG": {0, []byte{0x0F, 0x01}, 7},
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}
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// movbeSize maps the MOVBE spellings to their operand size.
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var movbeSize = map[string]int{
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"MOVBEW": 2,
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"MOVBEL": 4,
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"MOVBEQ": 8,
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}
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// randSource maps the random-source bases to their /digit (RDRAND /6,
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// RDSEED /7); the destination register rides r/m, mod 11.
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var randSource = map[string]int{
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"RDRAND": 6,
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"RDSEED": 7,
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}
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// fsGsBase maps the FS/GS base accessors to their /digit in the F3-prefixed
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// 0F AE group; the L and Q spellings exist.
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var fsGsBase = map[string]int{
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"RDFSBASE": 0,
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"RDGSBASE": 1,
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"WRFSBASE": 2,
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"WRGSBASE": 3,
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}
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// descTable maps the descriptor-table accesses to their /digit in 0F 01;
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// each takes one memory operand alone.
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var descTable = map[string]int{
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"LGDT": 2,
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"LIDT": 3,
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"SGDT": 0,
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"SIDT": 1,
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}
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// sysRmEntry is one 0F 00/01 register-or-memory access. sized marks the
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// members whose trailing width letter (SLDTW, STRQ, SMSWL) carries the width
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// prefix ladder; the rest are fixed-width single names.
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type sysRmEntry struct {
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group byte
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digit int
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sized bool
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}
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// sysRm maps the system register accesses LLDT/LTR/VERR/VERW/SLDT/STR (group
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// 0F 00), LMSW/SMSW (0F 01).
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var sysRm = map[string]sysRmEntry{
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"LLDT": {0x00, 2, false},
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"LTR": {0x00, 3, false},
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"VERR": {0x00, 4, false},
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"VERW": {0x00, 5, false},
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"SLDT": {0x00, 0, true},
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"STR": {0x00, 1, true},
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"LMSW": {0x01, 6, false},
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"SMSW": {0x01, 4, true},
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}
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// selectorRead maps the selector reads LAR and LSL to their opcodes; both
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// load the destination register from an r/m selector, width prefixes per the
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// suffix.
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var selectorRead = map[string]byte{
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"LAR": 0x02,
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"LSL": 0x03,
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}
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// farSegLoad maps the far-segment loads to their opcodes; memory source
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// alone, destination register, width prefixes per the suffix.
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var farSegLoad = map[string]byte{
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"LFS": 0xB4,
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"LGS": 0xB5,
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"LSS": 0xB2,
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}
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// encodeSystem encodes the system, flag, string and segment families. It
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// reports whether the mnemonic belongs to the family.
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func (e *enc) encodeSystem(upper string, ops []Operand) (bool, error) {
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if op, ok := systemNoOperand[upper]; ok {
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if len(ops) != 0 {
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return true, fmt.Errorf("%s takes no operands, got %d", upper, len(ops))
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}
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return true, e.emit(&instr{opcode: append([]byte(nil), op...), modrm: -1, sib: -1})
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}
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// The string primitives carry a B/W/L/Q suffix only; CMPSD and friends
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// are the SSE compare family's names and must reach their own dispatch.
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if b, size := splitSize(upper); size != 0 {
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switch upper[len(upper)-1] {
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case 'B', 'W', 'L', 'Q':
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if op32, ok := stringOp[b]; ok {
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return true, e.encodeSystemString(upper, op32, ops)
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}
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}
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}
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if size, ok := nopWidth[upper]; ok {
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if len(ops) != 1 {
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return true, fmt.Errorf("%s expects 1 operand, got %d", upper, len(ops))
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}
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i := newInstr(size, []byte{0x0F, 0x1F})
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if err := setRMDigit(i, 0, ops[0], size); err != nil {
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return true, err
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}
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return true, e.emit(i)
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}
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if m, ok := cacheControl[upper]; ok {
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if len(ops) != 1 {
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return true, fmt.Errorf("%s expects 1 memory operand, got %d", upper, len(ops))
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}
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if !isX86Mem(ops[0]) {
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return true, fmt.Errorf("%s requires a memory operand", upper)
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}
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i := &instr{prefix: m.prefix, opcode: m.op, modrm: -1, sib: -1}
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if err := setRMDigit(i, m.digit, ops[0], 8); err != nil {
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return true, err
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}
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return true, e.emit(i)
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}
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if _, ok := movbeSize[upper]; ok {
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return true, e.encodeSystemMovbe(upper, ops)
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}
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if digit, ok := randSource[base(upper, 6)]; ok {
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return true, e.encodeSystemRand(upper, digit, ops)
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}
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if digit, ok := fsGsBase[base(upper, 8)]; ok {
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return true, e.encodeSystemFsGsBase(upper, digit, ops)
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}
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if digit, ok := descTable[upper]; ok {
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if len(ops) != 1 {
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return true, fmt.Errorf("%s expects 1 memory operand, got %d", upper, len(ops))
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}
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if !isX86Mem(ops[0]) {
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return true, fmt.Errorf("%s requires a memory operand", upper)
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}
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i := &instr{opcode: []byte{0x0F, 0x01}, modrm: -1, sib: -1}
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if err := setRMDigit(i, digit, ops[0], 8); err != nil {
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return true, err
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}
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return true, e.emit(i)
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}
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if m, ok := sysRm[upper]; ok {
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return true, e.encodeSystemRm(upper, m, ops)
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}
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if b, size := splitSize(upper); size != 0 {
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if m, ok := sysRm[b]; ok && m.sized {
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return true, e.encodeSystemRm(upper, m, ops)
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}
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}
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if op, ok := selectorRead[base(upper, 3)]; ok {
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return true, e.encodeSystemSelectorRead(upper, op, ops)
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}
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if op, ok := farSegLoad[base(upper, 3)]; ok {
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return true, e.encodeSystemFarLoad(upper, op, ops)
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}
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if upper == "CMPXCHG8B" || upper == "CMPXCHG16B" {
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if len(ops) != 1 {
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return true, fmt.Errorf("%s expects 1 memory operand, got %d", upper, len(ops))
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}
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if !isX86Mem(ops[0]) {
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return true, fmt.Errorf("%s requires a memory operand", upper)
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}
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i := newInstr(0, []byte{0x0F, 0xC7})
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i.rexW = upper == "CMPXCHG16B"
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if err := setRMDigit(i, 1, ops[0], 8); err != nil {
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return true, err
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}
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return true, e.emit(i)
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}
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return false, nil
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}
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// base returns the first n characters of an upper-case mnemonic, or the empty
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// string when the mnemonic is shorter: the safe head lookup for the families
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// whose width suffix rides the tail (RDRANDW, RDFSBASEQ, LARW).
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func base(upper string, n int) string {
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if len(upper) <= n {
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return ""
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}
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return upper[:n]
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}
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// encodeSystemString encodes a string primitive: no operands, the width
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// suffix picks the byte form, the 0x66 prefix or REX.W. Only the B/W/L/Q
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// suffixes belong to the family: CMPSD and friends are the SSE compare
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// family's names and must reach their own dispatch.
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func (e *enc) encodeSystemString(upper string, op32 byte, ops []Operand) error {
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switch upper[len(upper)-1] {
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case 'B', 'W', 'L', 'Q':
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default:
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return fmt.Errorf("unsupported instruction %q", upper)
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}
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b, size := splitSize(upper)
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if _, ok := stringOp[b]; !ok || size == 0 {
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return fmt.Errorf("unsupported instruction %q", upper)
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}
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if len(ops) != 0 {
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return fmt.Errorf("%s takes no operands, got %d", upper, len(ops))
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}
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// The byte spelling is the 32-bit opcode minus one; the W and Q forms
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// ride newInstr's prefix ladder, the L form the bare opcode.
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op := op32
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if size == 1 {
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op--
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}
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return e.emit(newInstr(size, []byte{op}))
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}
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// encodeSystemMovbe encodes MOVBE: a register source stores (F1, reg = the
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// register, r/m = memory), a register destination loads (F0, same fields).
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func (e *enc) encodeSystemMovbe(mnem string, ops []Operand) error {
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size := movbeSize[mnem]
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if len(ops) != 2 {
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return fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
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}
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srcReg, srcIsReg := ops[0].(Reg)
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dstReg, dstIsReg := ops[1].(Reg)
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var op byte
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var reg Reg
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var rm Operand
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switch {
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case srcIsReg && isX86Mem(ops[1]):
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op, reg, rm = 0xF1, srcReg, ops[1] // store
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case dstIsReg && isX86Mem(ops[0]):
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op, reg, rm = 0xF0, dstReg, ops[0] // load
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default:
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return fmt.Errorf("%s takes one register and one memory operand", mnem)
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}
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i := newInstr(size, []byte{0x0F, 0x38, op})
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if err := setRM(i, reg, rm, size); err != nil {
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return err
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}
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return e.emit(i)
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}
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// encodeSystemRand encodes RDRAND/RDSEED: the single register operand rides
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// r/m under the /digit, mod 11, with the width prefix the suffix picks.
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func (e *enc) encodeSystemRand(mnem string, digit int, ops []Operand) error {
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b, size := splitSize(mnem)
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if _, ok := randSource[b]; !ok || size == 0 {
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return fmt.Errorf("unsupported instruction %q", mnem)
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}
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if len(ops) != 1 {
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return fmt.Errorf("%s expects 1 register operand, got %d", mnem, len(ops))
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}
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dstReg, ok := ops[0].(Reg)
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if !ok || dstReg.isVec() {
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return fmt.Errorf("%s destination must be a general register", mnem)
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}
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i := newInstr(size, []byte{0x0F, 0xC7})
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if err := setRMDigit(i, digit, dstReg, size); err != nil {
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return err
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}
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return e.emit(i)
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}
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// encodeSystemFsGsBase encodes the FS/GS base accessors: F3-prefixed 0F AE
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// under the /digit, the register in r/m; the Q spellings add REX.W.
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func (e *enc) encodeSystemFsGsBase(mnem string, digit int, ops []Operand) error {
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b, size := splitSize(mnem)
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if _, ok := fsGsBase[b]; !ok || (size != 4 && size != 8) {
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return fmt.Errorf("unsupported instruction %q", mnem)
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}
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if len(ops) != 1 {
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return fmt.Errorf("%s expects 1 register operand, got %d", mnem, len(ops))
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}
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dstReg, ok := ops[0].(Reg)
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if !ok || dstReg.isVec() {
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return fmt.Errorf("%s destination must be a general register", mnem)
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}
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i := newInstr(0, []byte{0x0F, 0xAE})
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i.prefix = 0xF3
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i.rexW = size == 8
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if err := setRMDigit(i, digit, dstReg, 8); err != nil {
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return err
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}
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return e.emit(i)
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}
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// encodeSystemRm encodes a 0F 00/01 r/m access: the operand is a register or
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// memory; the sized members carry the width prefix ladder the suffix fixes.
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func (e *enc) encodeSystemRm(mnem string, m sysRmEntry, ops []Operand) error {
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size := 0
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if m.sized {
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_, size = splitSize(mnem)
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if size == 0 {
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return fmt.Errorf("unsupported instruction %q", mnem)
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}
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}
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if len(ops) != 1 {
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return fmt.Errorf("%s expects 1 operand, got %d", mnem, len(ops))
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}
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i := newInstr(size, []byte{0x0F, m.group})
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if err := setRMDigit(i, m.digit, ops[0], size); err != nil {
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return err
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}
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return e.emit(i)
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}
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// encodeSystemSelectorRead encodes LAR/LSL: the destination register loads
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// from an r/m selector, width prefixes per the suffix.
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func (e *enc) encodeSystemSelectorRead(mnem string, op byte, ops []Operand) error {
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b, size := splitSize(mnem)
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if _, ok := selectorRead[b]; !ok || size == 0 {
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return fmt.Errorf("unsupported instruction %q", mnem)
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}
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if len(ops) != 2 {
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return fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
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}
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dstReg, ok := ops[1].(Reg)
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if !ok || dstReg.isVec() {
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return fmt.Errorf("%s destination must be a general register", mnem)
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}
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i := newInstr(size, []byte{0x0F, op})
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if err := setRM(i, dstReg, ops[0], size); err != nil {
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return err
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}
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return e.emit(i)
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}
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// encodeSystemFarLoad encodes LFS/LGS/LSS: the destination register loads a
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// far pointer from memory, width prefixes per the suffix.
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func (e *enc) encodeSystemFarLoad(mnem string, op byte, ops []Operand) error {
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||||
b, size := splitSize(mnem)
|
||||
if _, ok := farSegLoad[b]; !ok || size == 0 {
|
||||
return fmt.Errorf("unsupported instruction %q", mnem)
|
||||
}
|
||||
if len(ops) != 2 {
|
||||
return fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
if !isX86Mem(ops[0]) {
|
||||
return fmt.Errorf("%s requires a memory source", mnem)
|
||||
}
|
||||
dstReg, ok := ops[1].(Reg)
|
||||
if !ok || dstReg.isVec() {
|
||||
return fmt.Errorf("%s destination must be a general register", mnem)
|
||||
}
|
||||
i := newInstr(size, []byte{0x0F, op})
|
||||
if err := setRM(i, dstReg, ops[0], size); err != nil {
|
||||
return err
|
||||
}
|
||||
return e.emit(i)
|
||||
}
|
||||
Reference in new issue
Block a user