feat(arch): encode the amd64 embedded rounding and SAE decorations
Assisted-by: GLM 5.3
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@@ -9,26 +9,31 @@
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// for every mnemonic here, so the layer stays out of the main encoders.
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//
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// The families are AVX512-BF16, AVX512-VP2INTERSECT and AVX512-FP16, the
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// latter's scalar core with its imm8-control group and its packed 512-bit
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// arithmetic, in their EVEX register forms. The encodings are transcribed
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// from the SDM instruction entries and cross-checked against binutils-gdb's
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// assembler testsuite; the golden vectors in amd64_ext_test.go pin the
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// bytes. VPOPCNTD and VPOPCNTQ, the third family of the 2026-09-19 survey,
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// no longer belong here: the Go toolchain's assembler knows them today, they
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// latter's scalar core with its imm8-control group, its packed 512-bit and
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// VL arithmetic and the embedded rounding of its FP operations, in their
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// EVEX register forms. The encodings are transcribed from the SDM
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// instruction entries and cross-checked against binutils-gdb's assembler
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// testsuite; the golden vectors in amd64_ext_test.go pin the bytes.
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// VPOPCNTD and VPOPCNTQ, the third family of the 2026-09-19 survey, no
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// longer belong here: the Go toolchain's assembler knows them today, they
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// live in the generated table and the EVEX encoder, and a mnemonic the
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// toolchain has is not an extension.
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//
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// The forms encode the unmasked shapes: register forms throughout, and the
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// memory forms beside them, the scalar ones the manual spells m16 and the
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// packed ones with the {1toN} broadcast, base-relative operands with the
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// ModR/M disp8 and disp32 choices and the SIB byte RSP and R12 demand, the
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// scaled index and the broadcast laying the SIB byte and EVEX.b over the
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// same displacement semantics. The packed destinations take the write mask
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// beside all of it, the {k1}{z} decorations the SDM spells: EVEX.aaa carries
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// the masking register and EVEX.z the zeroing bit, K0 masks nothing, and the
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// scalar forms, the compares, the opmask destinations and the load and store
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// shapes take no mask at all. Embedded rounding still arrives with a later
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// slice.
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// memory forms beside them, the scalar ones the manual spells m16, m32 and
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// m64 and the packed ones with the {1toN} broadcast, base-relative operands
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// with the ModR/M disp8 and disp32 choices and the SIB byte RSP and R12
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// demand, the scaled index and the broadcast laying the SIB byte and EVEX.b
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// over the same displacement semantics. The packed destinations take the
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// write mask beside all of it, the {k1}{z} decorations the SDM spells:
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// EVEX.aaa carries the masking register and EVEX.z the zeroing bit, K0 masks
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// nothing, and the scalar forms, the compares, the opmask destinations and
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// the load and store shapes take no mask at all. The FP destinations take
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// the embedded rounding beside that, the {sae} and {rn-sae} through
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// {rz-sae} decorations: EVEX.b selects the rounding context and EVEX.RC,
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// the L'L bits it replaces, the mode, on the 512-bit and scalar register
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// forms alone, exactly the two lengths whose word has no vector length left
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// to lose.
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package arch
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@@ -159,6 +164,9 @@ func (in ExtInstr) amd64Memory(op ExtOperand, pos int) (base int, disp int64, er
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if op.HasShift {
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return 0, 0, fmt.Errorf("%s: operand %d carries a shift, the amd64 memory forms take none", in.Name, pos)
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}
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if op.Round != ExtRoundNone {
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return 0, 0, fmt.Errorf("%s: operand %d carries a rounding control, the memory operand takes none", in.Name, pos)
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}
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if op.Broadcast && !in.Bcast {
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return 0, 0, fmt.Errorf("%s: operand %d carries a broadcast, the entry's memory operand takes none", in.Name, pos)
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}
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@@ -307,27 +315,63 @@ func (in ExtInstr) amd64MemBytes(b []byte, dest, vvvv int, op ExtOperand, pos in
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return amd64EncodeMemory(b, dest, vvvv, base, disp), nil
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}
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// amd64WriteMask lifts the write mask spelling out of a destination operand:
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// the returned copy carries the register bits alone, the mask register and
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// the zeroing flag come back beside it. K0 never masks, zeroing is valid
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// only beside a mask, and an entry whose destination takes none refuses the
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// spellings outright, so nothing arrives at the encoding half-claimed.
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func (in ExtInstr) amd64WriteMask(op ExtOperand, pos int) (ExtOperand, int, bool, error) {
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// amd64WriteMask lifts the decorations off a destination operand: the
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// returned copy carries the register bits alone, while the mask register,
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// the zeroing flag and the rounding control come back beside it. K0 never
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// masks, zeroing is valid only beside a mask, and an entry whose destination
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// takes neither decoration refuses the spellings outright, so nothing
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// arrives at the encoding half-claimed. The rounding decoration is
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// validated against the entry's capability: an entry that carries neither
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// Er nor Sae takes none, an Er entry demands one of the four modes, and an
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// entry that suppresses exceptions alone takes {sae} and refuses every
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// mode, the split the manual's two decoration classes draw.
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func (in ExtInstr) amd64WriteMask(op ExtOperand, pos int) (ExtOperand, int, bool, ExtRounding, error) {
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stripped := op
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stripped.Mask, stripped.HasMask, stripped.Zeroing = 0, false, false
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if !op.HasMask && !op.Zeroing {
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return stripped, 0, false, nil
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round := op.Round
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stripped.Round = ExtRoundNone
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if !op.HasMask && !op.Zeroing && round == ExtRoundNone {
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return stripped, 0, false, ExtRoundNone, nil
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}
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if !in.Mask {
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return stripped, 0, false, fmt.Errorf("%s: operand %d carries a write mask, the entry's destination takes none", in.Name, pos)
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if op.HasMask || op.Zeroing {
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if !in.Mask {
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return stripped, 0, false, round, fmt.Errorf("%s: operand %d carries a write mask, the entry's destination takes none", in.Name, pos)
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}
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if !op.HasMask {
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return stripped, 0, false, round, fmt.Errorf("%s: operand %d carries zeroing without a write mask", in.Name, pos)
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}
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if op.Mask < 1 || op.Mask > 7 {
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return stripped, 0, false, round, fmt.Errorf("%s: operand %d names write mask k%d, outside the masking registers k1-k7", in.Name, pos, op.Mask)
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}
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}
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if !op.HasMask {
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return stripped, 0, false, fmt.Errorf("%s: operand %d carries zeroing without a write mask", in.Name, pos)
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if round != ExtRoundNone {
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if !in.Er && !in.Sae {
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return stripped, 0, false, round, fmt.Errorf("%s: operand %d carries a rounding control, the entry's destination takes none", in.Name, pos)
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}
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if in.Sae && round != ExtRoundSAE {
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return stripped, 0, false, round, fmt.Errorf("%s: operand %d names the rounding mode %s, the entry suppresses exceptions alone and takes {sae}", in.Name, pos, round)
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}
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if in.Er && round == ExtRoundSAE {
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return stripped, 0, false, round, fmt.Errorf("%s: operand %d spells {sae} without a mode, the embedded rounding wants {rn-sae} through {rz-sae}", in.Name, pos)
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}
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}
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if op.Mask < 1 || op.Mask > 7 {
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return stripped, 0, false, fmt.Errorf("%s: operand %d names write mask k%d, outside the masking registers k1-k7", in.Name, pos, op.Mask)
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return stripped, op.Mask, op.Zeroing, round, nil
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}
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// amd64ApplyRounding lays the validated rounding decoration into the encoded
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// word: EVEX.b, bit four of byte three, selects the rounding context, and
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// EVEX.RC, the L'L bits, names the mode. The L'L bits the template carries
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// are cleared, because a word with an embedded rounding mode has no vector
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// length of its own to spell; the write mask keeps its bits under the
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// decoration, EVEX.aaa and EVEX.z untouched. An undecorated destination
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// leaves the word alone: its L'L carries the vector length.
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func amd64ApplyRounding(b []byte, mode ExtRounding) {
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if mode == ExtRoundNone {
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return
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}
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return stripped, op.Mask, op.Zeroing, nil
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b[3] &^= 0x60
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b[3] |= 0x10
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b[3] |= amd64RoundingBits(mode) << 5
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}
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// amd64ApplyMask lays the validated write mask into the encoded word:
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@@ -361,6 +405,9 @@ func (in ExtInstr) amd64PlainReg(op ExtOperand, max, pos int) error {
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if op.Zeroing {
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return fmt.Errorf("%s: operand %d carries zeroing, the position takes none", in.Name, pos)
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}
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if op.Round != ExtRoundNone {
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return fmt.Errorf("%s: operand %d carries a rounding control, the position takes none", in.Name, pos)
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}
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if op.Arr != ExtArrNone {
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return fmt.Errorf("%s: operand %d carries an arrangement suffix, the amd64 layer takes none", in.Name, pos)
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}
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@@ -442,17 +489,23 @@ func (in ExtInstr) encodeAmd64(ops []ExtOperand) ([]byte, error) {
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// arithmetic, spelled xmm3/m16 in the manual, may be a base-relative
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// operand, which rides the r/m field with its displacement bytes after the
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// opcode, and the packed entries lay the source's {1toN} broadcast over the
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// same encoding as EVEX.b.
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// same encoding as EVEX.b. An entry with Er or Sae set takes the rounding
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// decoration on its register form alone: the memory shape refuses one, the
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// embedded rounding and the broadcast share EVEX.b and cannot ride the same
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// word.
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func (in ExtInstr) encodeAmdVec3(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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if err := in.amd64Vector(ops[0], class, 1); err != nil {
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return nil, err
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}
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if in.Mem == 2 && ops[1].Kind == ExtMem {
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dest, mask, zeroing, err := in.amd64WriteMask(ops[2], 3)
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dest, mask, zeroing, round, err := in.amd64WriteMask(ops[2], 3)
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if err != nil {
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return nil, err
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}
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if round != ExtRoundNone {
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return nil, fmt.Errorf("%s: the memory form takes no rounding control, the decoration belongs to the register form", in.Name)
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}
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if err := in.amd64Vector(dest, class, 3); err != nil {
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return nil, err
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}
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@@ -468,7 +521,7 @@ func (in ExtInstr) encodeAmdVec3(ops []ExtOperand) ([]byte, error) {
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return nil, err
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}
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}
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dest, mask, zeroing, err := in.amd64WriteMask(ops[2], 3)
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dest, mask, zeroing, round, err := in.amd64WriteMask(ops[2], 3)
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if err != nil {
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return nil, err
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}
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@@ -477,6 +530,7 @@ func (in ExtInstr) encodeAmdVec3(ops []ExtOperand) ([]byte, error) {
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}
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out := amd64Encode(in.Bytes, dest.Reg, ops[0].Reg, ops[1].Reg)
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amd64ApplyMask(out, mask, zeroing)
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amd64ApplyRounding(out, round)
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return out, nil
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}
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@@ -507,27 +561,32 @@ func (in ExtInstr) encodeAmdVecMem(ops []ExtOperand) ([]byte, error) {
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// encodeAmdVec2 fills the two-vector form: src, dest. The half form narrows
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// the destination: VCVTNEPS2BF16 converts 512 bits of source into 256 bits
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// of destination, and at 128 bits the companion stays the class itself. An
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// entry with Mem set takes the memory shape of that position too: the
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// entry with Mem set takes the memory shape of the source position too: the
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// compares and the packed square root read their source from memory, the
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// packed square root's source carrying the {1toN} broadcast as EVEX.b, and
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// the narrow BF16 convert reads its full-width source there.
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// the narrow BF16 convert reads its full-width source there. An entry with
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// Er or Sae set takes the rounding decoration on its register form alone;
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// the memory shape refuses one.
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func (in ExtInstr) encodeAmdVec2(ops []ExtOperand) ([]byte, error) {
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class := amd64LengthClass(in.Bytes)
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destClass := class
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if in.Form == ExtFormAmdVec2Half {
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destClass = amd64HalfClass(class)
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}
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dest, mask, zeroing, err := in.amd64WriteMask(ops[1], 2)
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dest, mask, zeroing, round, err := in.amd64WriteMask(ops[1], 2)
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if err != nil {
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return nil, err
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}
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if in.Mem == 1 && ops[0].Kind == ExtMem {
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// The memory spelling is validated before the destination: on the
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// half form the destination's narrowed class is the likelier
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// narrow form the destination's narrowed class is the likelier
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// rejection, but a miswritten source spelling names itself first.
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if _, _, err := in.amd64Memory(ops[0], 1); err != nil {
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return nil, err
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}
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if round != ExtRoundNone {
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return nil, fmt.Errorf("%s: the memory form takes no rounding control, the decoration belongs to the register form", in.Name)
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}
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if err := in.amd64Vector(dest, destClass, 2); err != nil {
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return nil, err
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}
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@@ -538,17 +597,6 @@ func (in ExtInstr) encodeAmdVec2(ops []ExtOperand) ([]byte, error) {
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amd64ApplyMask(out, mask, zeroing)
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return out, nil
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}
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if in.Mem == 2 && ops[1].Kind == ExtMem {
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if err := in.amd64Vector(ops[0], class, 1); err != nil {
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return nil, err
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}
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out, err := in.amd64MemBytes(in.Bytes, ops[0].Reg, -1, dest, 2)
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if err != nil {
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return nil, err
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}
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amd64ApplyMask(out, mask, zeroing)
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return out, nil
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}
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if err := in.amd64Vector(ops[0], class, 1); err != nil {
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return nil, err
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}
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@@ -557,6 +605,7 @@ func (in ExtInstr) encodeAmdVec2(ops []ExtOperand) ([]byte, error) {
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}
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out := amd64Encode(in.Bytes, dest.Reg, -1, ops[0].Reg)
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amd64ApplyMask(out, mask, zeroing)
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amd64ApplyRounding(out, round)
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return out, nil
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}
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@@ -601,6 +650,9 @@ func (in ExtInstr) amd64Imm8(op ExtOperand, pos int) (byte, error) {
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if op.Zeroing {
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return 0, fmt.Errorf("%s: operand %d carries zeroing, the immediate takes none", in.Name, pos)
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}
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if op.Round != ExtRoundNone {
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return 0, fmt.Errorf("%s: operand %d carries a rounding control, the immediate takes none", in.Name, pos)
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}
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if op.Imm < 0 || op.Imm > 255 {
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return 0, fmt.Errorf("%s: operand %d is immediate %d, outside the unsigned byte range 0-255", in.Name, pos, op.Imm)
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}
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@@ -676,7 +728,7 @@ func (in ExtInstr) encodeAmdMask2Imm(ops []ExtOperand) ([]byte, error) {
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return append(out, imm), nil
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}
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// ExtFP16RoundingModes names the two-bit rounding mode the round control of
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// ExtRoundingMode names the two-bit rounding mode the round control of
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// VRNDSCALESH and VREDUCESH carries, indexed by imm8[1:0], the SDM's RC
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// field encoding.
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var ExtFP16RoundingModes = [4]string{
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@@ -686,6 +738,87 @@ var ExtFP16RoundingModes = [4]string{
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"round toward zero (truncate)",
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}
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// ExtRounding names the rounding decoration an FP destination of the amd64
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// layer carries, the SDM's {sae} and {rn-sae} through {rz-sae} spellings.
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// The decoration is the EVEX embedded rounding: EVEX.b, bit four of byte
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// three, selects the rounding context, and EVEX.RC, the two bits above it
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// that carry L'L in every other word, names the mode, in the very encoding
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// the imm8 round control uses: 00 round to nearest even, 01 down toward
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// negative infinity, 10 up toward positive infinity, 11 toward zero. The
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// L'L bits the template carries are cleared when the decoration applies,
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// which is why only the 512-bit and the scalar forms take one: a word with
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// an embedded mode has no vector length of its own to spell. ExtRoundSAE
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// suppresses the floating-point exceptions alone and leaves EVEX.RC zero;
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// the entries that take it (Er) demand a mode, the entries that take SAE
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// alone refuse every mode, exactly the split the manual's two decoration
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// classes draw.
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type ExtRounding uint8
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// The rounding decorations, ExtRoundNone first as the zero value every
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// undecorated destination carries.
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const (
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// ExtRoundNone marks a destination without a rounding decoration: the
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// MXCSR rules govern the operation.
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ExtRoundNone ExtRounding = iota
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// ExtRoundSAE is {sae}: suppress all floating-point exceptions, no mode
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// named.
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ExtRoundSAE
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// ExtRoundNearest is {rn-sae}: round to nearest, ties to even, EVEX.RC 00.
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ExtRoundNearest
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// ExtRoundDown is {rd-sae}: round down toward negative infinity, EVEX.RC 01.
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ExtRoundDown
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// ExtRoundUp is {ru-sae}: round up toward positive infinity, EVEX.RC 10.
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ExtRoundUp
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// ExtRoundTruncate is {rz-sae}: round toward zero, EVEX.RC 11.
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ExtRoundTruncate
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)
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// String returns the spelling the decoration carries in the reference
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// listings, for diagnostics.
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func (r ExtRounding) String() string {
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switch r {
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case ExtRoundSAE:
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return "{sae}"
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case ExtRoundNearest:
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return "{rn-sae}"
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case ExtRoundDown:
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return "{rd-sae}"
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case ExtRoundUp:
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return "{ru-sae}"
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case ExtRoundTruncate:
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return "{rz-sae}"
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default:
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return "no rounding control"
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}
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}
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// amd64RoundingBits lays the decoration's EVEX.RC encoding out: the four
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// named modes in the SDM's RC field order, and {sae}, which names no mode,
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// as the nearest-even bits the exception suppression shares.
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func amd64RoundingBits(r ExtRounding) byte {
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switch r {
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case ExtRoundDown:
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return 1
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case ExtRoundUp:
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return 2
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case ExtRoundTruncate:
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return 3
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default:
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return 0
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}
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}
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// ExtRounded builds the rounded spelling of an FP destination, ZMM1{k7}{z},
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// {rz-sae} style: the operation rounds by the named mode instead of the
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// MXCSR, or suppresses its exceptions under {sae}. The mode rides the
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// destination operand beside the write mask, the two decorations the
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// reference listings spell on the one line; they compose, EVEX.aaa and
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// EVEX.z keeping their bits under EVEX.RC.
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func ExtRounded(dest ExtOperand, mode ExtRounding) ExtOperand {
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dest.Round = mode
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return dest
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}
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// ExtFP16GetMantSigns names the sign control imm8[3:2] of the VGETMANTSH
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// immediate, indexed by the field: the source's own sign, a forced positive,
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// and the two encodings that yield the indefinite NaN on a negative source.
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@@ -709,25 +842,36 @@ var ExtFP16CmpPredicates = [32]string{
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// encodeAmdVecGprVec fills the conversion form with a general-register
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// source: src1, gpr, dest. VCVTSI2SH X1, X2, EAX style. An entry with Mem
|
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// set takes the memory shape of the integer source, which the manual spells
|
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// r/m32: the value converts straight out of memory.
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// r/m32: the value converts straight out of memory. The register form takes
|
||||
// the rounding decoration the integer converts carry; the memory shape
|
||||
// refuses one.
|
||||
func (in ExtInstr) encodeAmdVecGprVec(ops []ExtOperand) ([]byte, error) {
|
||||
class := amd64LengthClass(in.Bytes)
|
||||
if err := in.amd64Vector(ops[0], class, 1); err != nil {
|
||||
return nil, err
|
||||
}
|
||||
dest, _, _, round, err := in.amd64WriteMask(ops[2], 3)
|
||||
if err != nil {
|
||||
return nil, err
|
||||
}
|
||||
if in.Mem == 2 && ops[1].Kind == ExtMem {
|
||||
if err := in.amd64Vector(ops[2], class, 3); err != nil {
|
||||
if round != ExtRoundNone {
|
||||
return nil, fmt.Errorf("%s: the memory form takes no rounding control, the decoration belongs to the register form", in.Name)
|
||||
}
|
||||
if err := in.amd64Vector(dest, class, 3); err != nil {
|
||||
return nil, err
|
||||
}
|
||||
return in.amd64MemBytes(in.Bytes, ops[2].Reg, ops[0].Reg, ops[1], 2)
|
||||
return in.amd64MemBytes(in.Bytes, dest.Reg, ops[0].Reg, ops[1], 2)
|
||||
}
|
||||
if err := in.amd64Gpr(ops[1], 2); err != nil {
|
||||
return nil, err
|
||||
}
|
||||
if err := in.amd64Vector(ops[2], class, 3); err != nil {
|
||||
if err := in.amd64Vector(dest, class, 3); err != nil {
|
||||
return nil, err
|
||||
}
|
||||
return amd64Encode(in.Bytes, ops[2].Reg, ops[0].Reg, ops[1].Reg), nil
|
||||
out := amd64Encode(in.Bytes, dest.Reg, ops[0].Reg, ops[1].Reg)
|
||||
amd64ApplyRounding(out, round)
|
||||
return out, nil
|
||||
}
|
||||
|
||||
// encodeAmdGprPair fills the two-operand general-register forms: gpr, vec
|
||||
@@ -845,40 +989,40 @@ var amd64Extensions = []ExtInstr{
|
||||
Bytes: []byte{0x62, 0x05, 0x05, 0x00, 0x7E, 0xC0}, Form: ExtFormAmdVecMem, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VMOVW (EVEX.128.66.MAP5.WIG 7E /r, m16 destination)"},
|
||||
{Name: "VADDSH", Summary: "Add scalar FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x58, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x58, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VADDSH (EVEX.NDS.LIG.F3.MAP5.W0 58 /r)"},
|
||||
{Name: "VSUBSH", Summary: "Subtract scalar FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5C, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5C, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VSUBSH (EVEX.NDS.LIG.F3.MAP5.W0 5C /r)"},
|
||||
{Name: "VMULSH", Summary: "Multiply scalar FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x59, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x59, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VMULSH (EVEX.NDS.LIG.F3.MAP5.W0 59 /r)"},
|
||||
{Name: "VDIVSH", Summary: "Divide scalar FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5E, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5E, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VDIVSH (EVEX.NDS.LIG.F3.MAP5.W0 5E /r)"},
|
||||
{Name: "VMINSH", Summary: "Return the minimum of scalar FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5D, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5D, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Sae: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VMINSH (EVEX.NDS.LIG.F3.MAP5.W0 5D /r)"},
|
||||
{Name: "VMAXSH", Summary: "Return the maximum of scalar FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5F, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5F, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Sae: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VMAXSH (EVEX.NDS.LIG.F3.MAP5.W0 5F /r)"},
|
||||
{Name: "VSQRTSH", Summary: "Compute the square root of a scalar FP16 value",
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x51, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x51, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VSQRTSH (EVEX.NDS.LIG.F3.MAP5.W0 51 /r)"},
|
||||
{Name: "VSCALEFSH", Summary: "Scale a scalar FP16 value by the ratio of two others",
|
||||
Bytes: []byte{0x62, 0x06, 0x05, 0x00, 0x2D, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x06, 0x05, 0x00, 0x2D, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VSCALEFSH (EVEX.NDS.LIG.66.MAP6.W0 2D /r)"},
|
||||
{Name: "VGETEXPSH", Summary: "Convert the exponent of a scalar FP16 value to an FP16 value",
|
||||
Bytes: []byte{0x62, 0x06, 0x05, 0x00, 0x43, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x06, 0x05, 0x00, 0x43, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Sae: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VGETEXPSH (EVEX.NDS.LIG.66.MAP6.W0 43 /r)"},
|
||||
{Name: "VCOMISH", Summary: "Compare a scalar FP16 value and set EFLAGS",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x2F, 0xC0}, Form: ExtFormAmdVec2, Mem: 1, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x2F, 0xC0}, Form: ExtFormAmdVec2, Mem: 1, Sae: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VCOMISH (EVEX.LIG.MAP5.W0 2F /r)"},
|
||||
{Name: "VUCOMISH", Summary: "Unordered-compare a scalar FP16 value and set EFLAGS",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x2E, 0xC0}, Form: ExtFormAmdVec2, Mem: 1, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x2E, 0xC0}, Form: ExtFormAmdVec2, Mem: 1, Sae: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VUCOMISH (EVEX.LIG.MAP5.W0 2E /r)"},
|
||||
{Name: "VCVTSS2SH", Summary: "Convert one FP32 value to one FP16 value",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x1D, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x1D, 0xC0}, Form: ExtFormAmdVec3, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VCVTSS2SH (EVEX.NDS.LIG.MAP5.W0 1D /r)"},
|
||||
{Name: "VCVTSH2SS", Summary: "Convert a low FP16 value to an FP32 value",
|
||||
Bytes: []byte{0x62, 0x06, 0x04, 0x00, 0x13, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
||||
@@ -887,19 +1031,19 @@ var amd64Extensions = []ExtInstr{
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x5A, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VCVTSH2SD (EVEX.NDS.LIG.F3.MAP5.W0 5A /r)"},
|
||||
{Name: "VCVTSD2SH", Summary: "Convert one FP64 value to one FP16 value",
|
||||
Bytes: []byte{0x62, 0x05, 0x87, 0x00, 0x5A, 0xC0}, Form: ExtFormAmdVec3, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x87, 0x00, 0x5A, 0xC0}, Form: ExtFormAmdVec3, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VCVTSD2SH (EVEX.NDS.LIG.F2.MAP5.W1 5A /r)"},
|
||||
{Name: "VCVTSI2SH", Summary: "Convert one signed 32-bit integer to one FP16 value",
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x2A, 0xC0}, Form: ExtFormAmdVecGprVec, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x2A, 0xC0}, Form: ExtFormAmdVecGprVec, Mem: 2, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VCVTSI2SH (EVEX.NDS.LIG.F3.MAP5.W0 2A /r)"},
|
||||
{Name: "VCVTSI2SH", Summary: "Convert one signed 64-bit integer to one FP16 value",
|
||||
Bytes: []byte{0x62, 0x05, 0x86, 0x00, 0x2A, 0xC0}, Form: ExtFormAmdVecGprVec, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x86, 0x00, 0x2A, 0xC0}, Form: ExtFormAmdVecGprVec, Mem: 2, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VCVTSI2SH (EVEX.NDS.LIG.F3.MAP5.W1 2A /r)"},
|
||||
{Name: "VCVTUSI2SH", Summary: "Convert one unsigned 32-bit integer to one FP16 value",
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x7B, 0xC0}, Form: ExtFormAmdVecGprVec, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x7B, 0xC0}, Form: ExtFormAmdVecGprVec, Mem: 2, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VCVTUSI2SH (EVEX.NDS.LIG.F3.MAP5.W0 7B /r)"},
|
||||
{Name: "VCVTUSI2SH", Summary: "Convert one unsigned 64-bit integer to one FP16 value",
|
||||
Bytes: []byte{0x62, 0x05, 0x86, 0x00, 0x7B, 0xC0}, Form: ExtFormAmdVecGprVec, Mem: 2, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x86, 0x00, 0x7B, 0xC0}, Form: ExtFormAmdVecGprVec, Mem: 2, Er: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VCVTUSI2SH (EVEX.NDS.LIG.F3.MAP5.W1 7B /r)"},
|
||||
{Name: "VCVTSH2SI", Summary: "Convert a low FP16 value to a signed 32-bit integer",
|
||||
Bytes: []byte{0x62, 0x05, 0x06, 0x00, 0x2D, 0xC0}, Form: ExtFormAmdVecGpr, Feature: ExtFeatureFP16,
|
||||
@@ -920,7 +1064,7 @@ var amd64Extensions = []ExtInstr{
|
||||
// quoted from x86-64-avx512_fp16.d, the 256- and 128-bit ones from
|
||||
// avx512_fp16_vl.d, on the same low registers the suite uses.
|
||||
{Name: "VADDPH", Summary: "Add packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x58, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x58, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Er: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VADDPH (EVEX.NDS.512.MAP5.W0 58 /r)"},
|
||||
{Name: "VADDPH", Summary: "Add packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x20, 0x58, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
@@ -929,7 +1073,7 @@ var amd64Extensions = []ExtInstr{
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x58, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VADDPH (EVEX.NDS.128.MAP5.W0 58 /r)"},
|
||||
{Name: "VSUBPH", Summary: "Subtract packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x5C, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x5C, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Er: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VSUBPH (EVEX.NDS.512.MAP5.W0 5C /r)"},
|
||||
{Name: "VSUBPH", Summary: "Subtract packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x20, 0x5C, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
@@ -938,7 +1082,7 @@ var amd64Extensions = []ExtInstr{
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x5C, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VSUBPH (EVEX.NDS.128.MAP5.W0 5C /r)"},
|
||||
{Name: "VMULPH", Summary: "Multiply packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x59, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x59, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Er: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VMULPH (EVEX.NDS.512.MAP5.W0 59 /r)"},
|
||||
{Name: "VMULPH", Summary: "Multiply packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x20, 0x59, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
@@ -947,7 +1091,7 @@ var amd64Extensions = []ExtInstr{
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x59, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VMULPH (EVEX.NDS.128.MAP5.W0 59 /r)"},
|
||||
{Name: "VDIVPH", Summary: "Divide packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x5E, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x5E, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Er: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VDIVPH (EVEX.NDS.512.MAP5.W0 5E /r)"},
|
||||
{Name: "VDIVPH", Summary: "Divide packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x20, 0x5E, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
@@ -956,7 +1100,7 @@ var amd64Extensions = []ExtInstr{
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x5E, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VDIVPH (EVEX.NDS.128.MAP5.W0 5E /r)"},
|
||||
{Name: "VMINPH", Summary: "Return the minimum of packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x5D, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x5D, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Sae: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VMINPH (EVEX.NDS.512.MAP5.W0 5D /r)"},
|
||||
{Name: "VMINPH", Summary: "Return the minimum of packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x20, 0x5D, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
@@ -965,7 +1109,7 @@ var amd64Extensions = []ExtInstr{
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x5D, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VMINPH (EVEX.NDS.128.MAP5.W0 5D /r)"},
|
||||
{Name: "VMAXPH", Summary: "Return the maximum of packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x5F, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x5F, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Sae: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VMAXPH (EVEX.NDS.512.MAP5.W0 5F /r)"},
|
||||
{Name: "VMAXPH", Summary: "Return the maximum of packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x20, 0x5F, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
@@ -974,7 +1118,7 @@ var amd64Extensions = []ExtInstr{
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x00, 0x5F, 0xC0}, Form: ExtFormAmdVec3, Mem: 2, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VMAXPH (EVEX.NDS.128.MAP5.W0 5F /r)"},
|
||||
{Name: "VSQRTPH", Summary: "Compute the square root of packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x51, 0xC0}, Form: ExtFormAmdVec2, Mem: 1, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x40, 0x51, 0xC0}, Form: ExtFormAmdVec2, Mem: 1, Mask: true, Er: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
Ref: "Intel SDM Vol. 2C, VSQRTPH (EVEX.512.MAP5.W0 51 /r)"},
|
||||
{Name: "VSQRTPH", Summary: "Compute the square root of packed FP16 values",
|
||||
Bytes: []byte{0x62, 0x05, 0x04, 0x20, 0x51, 0xC0}, Form: ExtFormAmdVec2, Mem: 1, Mask: true, Bcast: true, Feature: ExtFeatureFP16,
|
||||
|
||||
Reference in new issue
Block a user