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feat(arch): encode the amd64 embedded rounding and SAE decorations

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Assisted-by: GLM 5.3
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petrbalvin committed 2026-10-07 13:51:48 +02:00
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commit fb6d01a7d0
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arch/amd64_ext_test.go
+135 -2
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@@ -551,6 +551,115 @@ var amd64GoldenRows = []amd64GoldenRow{
{"vsqrtph k3 zeroing", "VSQRTPH",
[]ExtOperand{ExtZmm(29), ExtWriteMasked(ExtZmm(30), 3, true)},
"62057ccb51f5", ""},
// The embedded rounding and the exception suppression, the EVEX.RC
// decorations the FP destinations of the 512-bit and the scalar register
// forms carry: EVEX.b selects the rounding context and EVEX.RC replaces
// L'L, naming the mode 00 nearest even through 11 toward zero in the very
// encoding the imm8 round control shares. Every row is quoted from the
// local GNU assembler's own output, whose FP16 table matches the SDM
// entry for entry; the AT&T listings spell the decoration ahead of the
// operands. The write mask composes under the decoration, its EVEX.aaa
// and EVEX.z bits untouched by EVEX.RC.
{"vaddph rn-sae", "VADDPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundNearest)},
"62f5541858f4", "62 f5 54 18 58 f4 vaddph {rn-sae},%zmm4,%zmm5,%zmm6"},
{"vaddph rd-sae", "VADDPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundDown)},
"62f5543858f4", "62 f5 54 38 58 f4 vaddph {rd-sae},%zmm4,%zmm5,%zmm6"},
{"vaddph ru-sae", "VADDPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundUp)},
"62f5545858f4", "62 f5 54 58 58 f4 vaddph {ru-sae},%zmm4,%zmm5,%zmm6"},
{"vaddph rz-sae", "VADDPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundTruncate)},
"62f5547858f4", "62 f5 54 78 58 f4 vaddph {rz-sae},%zmm4,%zmm5,%zmm6"},
{"vaddph rz-sae under k7", "VADDPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtWriteMasked(ExtZmm(6), 7, false), ExtRoundTruncate)},
"62f5547f58f4", "62 f5 54 7f 58 f4 vaddph {rz-sae},%zmm4,%zmm5,%zmm6{%k7}"},
{"vaddph rz-sae under k7, zeroing", "VADDPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtWriteMasked(ExtZmm(6), 7, true), ExtRoundTruncate)},
"62f554ff58f4", "62 f5 54 ff 58 f4 vaddph {rz-sae},%zmm4,%zmm5,%zmm6{%k7}{z}"},
{"vaddph rz-sae, high registers", "VADDPH",
[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtRounded(ExtZmm(30), ExtRoundTruncate)},
"6205147058f4", "62 05 14 70 58 f4 vaddph {rz-sae},%zmm28,%zmm29,%zmm30"},
{"vsubph rz-sae", "VSUBPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundTruncate)},
"62f554785cf4", "62 f5 54 78 5c f4 vsubph {rz-sae},%zmm4,%zmm5,%zmm6"},
{"vmulph rn-sae", "VMULPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundNearest)},
"62f5541859f4", "62 f5 54 18 59 f4 vmulph {rn-sae},%zmm4,%zmm5,%zmm6"},
{"vdivph rn-sae", "VDIVPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundNearest)},
"62f554185ef4", "62 f5 54 18 5e f4 vdivph {rn-sae},%zmm4,%zmm5,%zmm6"},
{"vminph sae", "VMINPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundSAE)},
"62f554185df4", "62 f5 54 18 5d f4 vminph {sae},%zmm4,%zmm5,%zmm6"},
{"vminph sae, high registers", "VMINPH",
[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtRounded(ExtZmm(30), ExtRoundSAE)},
"620514105df4", "62 05 14 10 5d f4 vminph {sae},%zmm28,%zmm29,%zmm30"},
{"vmaxph sae", "VMAXPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundSAE)},
"62f554185ff4", "62 f5 54 18 5f f4 vmaxph {sae},%zmm4,%zmm5,%zmm6"},
{"vsqrtph rz-sae", "VSQRTPH",
[]ExtOperand{ExtZmm(4), ExtRounded(ExtZmm(5), ExtRoundTruncate)},
"62f57c7851ec", "62 f5 7c 78 51 ec vsqrtph {rz-sae},%zmm4,%zmm5"},
{"vaddsh rn-sae", "VADDSH",
[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundNearest)},
"62f5561858f4", "62 f5 56 18 58 f4 vaddsh {rn-sae},%xmm4,%xmm5,%xmm6"},
{"vaddsh rz-sae, high registers", "VADDSH",
[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtRounded(ExtXmm(30), ExtRoundTruncate)},
"6205167058f4", "62 05 16 70 58 f4 vaddsh {rz-sae},%xmm28,%xmm29,%xmm30"},
{"vsubsh rd-sae", "VSUBSH",
[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundDown)},
"62f556385cf4", "62 f5 56 38 5c f4 vsubsh {rd-sae},%xmm4,%xmm5,%xmm6"},
{"vmulsh ru-sae", "VMULSH",
[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundUp)},
"62f5565859f4", "62 f5 56 58 59 f4 vmulsh {ru-sae},%xmm4,%xmm5,%xmm6"},
{"vdivsh rz-sae", "VDIVSH",
[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundTruncate)},
"62f556785ef4", "62 f5 56 78 5e f4 vdivsh {rz-sae},%xmm4,%xmm5,%xmm6"},
{"vminsh sae", "VMINSH",
[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundSAE)},
"62f556185df4", "62 f5 56 18 5d f4 vminsh {sae},%xmm4,%xmm5,%xmm6"},
{"vmaxsh sae", "VMAXSH",
[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundSAE)},
"62f556185ff4", "62 f5 56 18 5f f4 vmaxsh {sae},%xmm4,%xmm5,%xmm6"},
{"vsqrtsh rz-sae", "VSQRTSH",
[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundTruncate)},
"62f5567851f4", "62 f5 56 78 51 f4 vsqrtsh {rz-sae},%xmm4,%xmm5,%xmm6"},
{"vsqrtsh ru-sae, high registers", "VSQRTSH",
[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtRounded(ExtXmm(30), ExtRoundUp)},
"6205165051f4", "62 05 16 50 51 f4 vsqrtsh {ru-sae},%xmm28,%xmm29,%xmm30"},
{"vscalefsh rn-sae", "VSCALEFSH",
[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundNearest)},
"62f655182df4", "62 f6 55 18 2d f4 vscalefsh {rn-sae},%xmm4,%xmm5,%xmm6"},
{"vgetexpsh sae", "VGETEXPSH",
[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundSAE)},
"62f6551843f4", "62 f6 55 18 43 f4 vgetexpsh {sae},%xmm4,%xmm5,%xmm6"},
{"vcomish sae", "VCOMISH",
[]ExtOperand{ExtXmm(29), ExtRounded(ExtXmm(30), ExtRoundSAE)},
"62057c182ff5", "62 05 7c 18 2f f5 vcomish {sae},%xmm29,%xmm30"},
{"vucomish sae", "VUCOMISH",
[]ExtOperand{ExtXmm(29), ExtRounded(ExtXmm(30), ExtRoundSAE)},
"62057c182ef5", "62 05 7c 18 2e f5 vucomish {sae},%xmm29,%xmm30"},
{"vcvtss2sh rn-sae", "VCVTSS2SH",
[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundNearest)},
"62f554181df4", "62 f5 54 18 1d f4 vcvtss2sh {rn-sae},%xmm4,%xmm5,%xmm6"},
{"vcvtsd2sh rd-sae, high registers", "VCVTSD2SH",
[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtRounded(ExtXmm(30), ExtRoundDown)},
"620597305af4", "62 05 97 30 5a f4 vcvtsd2sh {rd-sae},%xmm28,%xmm29,%xmm30"},
{"vcvtsi2sh rn-sae, 32-bit", "VCVTSI2SH",
[]ExtOperand{ExtXmm(5), ExtGpr32(0), ExtRounded(ExtXmm(6), ExtRoundNearest)},
"62f556182af0", "62 f5 56 18 2a f0 vcvtsi2sh %eax,{rn-sae},%xmm5,%xmm6"},
{"vcvtsi2sh rz-sae, 64-bit, high registers", "VCVTSI2SH",
[]ExtOperand{ExtXmm(29), ExtGpr64(12), ExtRounded(ExtXmm(30), ExtRoundTruncate)},
"624596702af4", "62 45 96 70 2a f4 vcvtsi2sh %r12,{rz-sae},%xmm29,%xmm30"},
{"vcvtusi2sh ru-sae, 32-bit", "VCVTUSI2SH",
[]ExtOperand{ExtXmm(5), ExtGpr32(2), ExtRounded(ExtXmm(6), ExtRoundUp)},
"62f556587bf2", "62 f5 56 58 7b f2 vcvtusi2sh %edx,{ru-sae},%xmm5,%xmm6"},
{"vcvtusi2sh rd-sae, 64-bit, high registers", "VCVTUSI2SH",
[]ExtOperand{ExtXmm(29), ExtGpr64(12), ExtRounded(ExtXmm(30), ExtRoundDown)},
"624596307bf4", "62 45 96 30 7b f4 vcvtusi2sh %r12,{rd-sae},%xmm29,%xmm30"},
}
// amd64ResolveEntry finds the table entry a golden row exercises: the entry
@@ -767,8 +876,8 @@ func TestAmd64ExtRejects(t *testing.T) {
{"memory as the intersect source", "VP2INTERSECTD",
[]ExtOperand{ExtZmm(2), ExtMemory(9, 0), ExtMask(0)},
"wants a ZMM register"},
{"memory as the convert's source", "VCVTSS2SH",
[]ExtOperand{ExtXmm(28), ExtMemory(9, 0), ExtXmm(30)},
{"memory as the convert's first source", "VCVTSS2SH",
[]ExtOperand{ExtMemory(9, 0), ExtXmm(28), ExtXmm(30)},
"wants an XMM register"},
{"memory as the control byte", "VGETMANTSH",
[]ExtOperand{ExtMemory(9, 0), ExtXmm(28), ExtXmm(29), ExtXmm(30)},
@@ -830,6 +939,30 @@ func TestAmd64ExtRejects(t *testing.T) {
{"write mask where the destination is memory", "VCOMISH",
[]ExtOperand{ExtXmm(30), ExtOperand{Kind: ExtMem, Reg: 9, HasMask: true, Mask: 2}},
"the entry's destination takes none"},
{"rounding on the 256-bit arithmetic", "VADDPH",
[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtRounded(ExtYmm(6), ExtRoundNearest)},
"the entry's destination takes none"},
{"bare {sae} on the embedded-rounding arithmetic", "VADDPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundSAE)},
"spells {sae} without a mode"},
{"a named mode on the exception-suppressing minimum", "VMINPH",
[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundDown)},
"suppresses exceptions alone"},
{"rounding over a memory source", "VADDSH",
[]ExtOperand{ExtXmm(29), ExtMemory(9, 0), ExtRounded(ExtXmm(30), ExtRoundNearest)},
"the memory form takes no rounding control"},
{"rounding on a source position", "VADDPH",
[]ExtOperand{ExtZmm(5), ExtRounded(ExtZmm(4), ExtRoundUp), ExtZmm(6)},
"the position takes none"},
{"rounding on the control byte", "VRNDSCALESH",
[]ExtOperand{{Kind: ExtImm, Imm: 0x0b, Round: ExtRoundSAE}, ExtXmm(29), ExtXmm(28), ExtXmm(30)},
"the immediate takes none"},
{"rounding on the compare's memory operand", "VCOMISH",
[]ExtOperand{ExtOperand{Kind: ExtMem, Reg: 9, Round: ExtRoundSAE}, ExtXmm(30)},
"the memory operand takes none"},
{"rounding on an entry without the capability", "VMOVSH",
[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtRounded(ExtXmm(30), ExtRoundNearest)},
"the entry's destination takes none"},
} {
in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
_, err := in.Encode(tt.ops)