feat(arch): encode the amd64 embedded rounding and SAE decorations

Assisted-by: GLM 5.3

arch/arm64_ext.go

@@ -229,6 +229,12 @@ type ExtOperand struct {
 	BaseVec bool  // the first parenthesis spells a Z register
 	Extend  uint8 // 0 = none, 1 = UXTW, 2 = SXTW
 	Off     int   // the second parenthesis's register, -1 when absent
+	// Round spells the rounding decoration of an amd64 EVEX destination, the
+	// {sae} and {rn-sae} through {rz-sae} spellings: EVEX.b selects the
+	// rounding context and EVEX.RC, the L'L bits it replaces, the mode.  Only
+	// the destinations of the entries that carry Er or Sae accept it.  The
+	// arm64 entries all carry the zero value.
+	Round ExtRounding
 }
 
 // ExtVector builds a scalable vector operand, ADD Z1.S style.
@@ -967,6 +973,17 @@ type ExtInstr struct {
 	// opmask-destination forms and the load and store shapes do not.  The
 	// arm64 entries all carry the zero value.
 	Mask bool
+	// Er records that the entry's destination takes the embedded rounding
+	// decoration, the {rn-sae} through {rz-sae} spellings the FP arithmetic
+	// and the rounding conversions carry in their register forms: EVEX.b
+	// selects the rounding context, EVEX.RC names the mode, and the memory
+	// forms take none.  The arm64 entries all carry the zero value.
+	Er bool
+	// Sae records that the entry's destination takes the exception-suppression
+	// decoration alone, the {sae} spelling the minima, maxima, compares and
+	// exponent extracts carry: no mode is named and EVEX.RC stays zero.  The
+	// arm64 entries all carry the zero value.
+	Sae bool
 	// PgQual names the qualifier the row's governing predicate requires,
 	// where the form takes one: merging, zeroing or either (the MOVPRFX
 	// classes spell both with one encoding).  Forms without such a