petrbalvin
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7246b0e002
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feat(asm): the TLS access pair in the toolchain's one-instruction form
Assisted-by: GLM 5.3 Flash
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2026-09-21 21:35:15 +02:00 |
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petrbalvin
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8cfd40aac8
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feat(asm): the operand forms and defines GOROOT writes
Assisted-by: GLM 5.3 Flash
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2026-09-21 21:17:34 +02:00 |
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petrbalvin
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29ac03468e
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feat(amd64): floating-point immediates through a synthesised pool
Assisted-by: GLM 5.3 Flash
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2026-09-21 02:04:44 +02:00 |
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petrbalvin
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bfb7701db1
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feat(amd64): emit the quad-register EVEX families
Assisted-by: GLM 5.3 Flash
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2026-09-21 02:02:19 +02:00 |
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petrbalvin
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1456907000
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feat(riscv64,loong64): operand tail, float DATA and honest port classification
Assisted-by: GLM 5.3 Flash
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2026-09-21 00:44:47 +02:00 |
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petrbalvin
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522e6f2ae8
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feat(parser): bracket register ranges, index-only VSIB and bare trailing immediates
Assisted-by: GLM 5.3 Flash
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2026-09-20 22:02:19 +02:00 |
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petrbalvin
|
b0f9071bf5
|
feat(arm64): whole-vector moves, bookkeeping ops and truncating-move lowering
Assisted-by: GLM 5.3 Flash
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2026-09-20 21:17:20 +02:00 |
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petrbalvin
|
81e2673923
|
feat(amd64): encode the AVX-512 and BMI corpus families
Assisted-by: GLM 5.3 Flash
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2026-09-20 21:17:20 +02:00 |
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petrbalvin
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6556b85abf
|
feat(asm): symbol-valued DATA, division slash in symbols and plain semicolons
Assisted-by: GLM 5.3 Flash
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2026-09-20 19:15:05 +02:00 |
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petrbalvin
|
289cabe993
|
feat(loong64): encode the full LSX and LASX table
Assisted-by: GLM 5.3 Flash
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2026-09-20 19:14:43 +02:00 |
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petrbalvin
|
dce5d31462
|
feat(amd64): LOCK and REP prefixes, literal data pseudo-ops and ADJSP
Assisted-by: GLM 5.3 Flash
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2026-09-20 14:25:47 +02:00 |
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petrbalvin
|
9dc3987e02
|
feat(riscv64,loong64): PCALIGN, branch relaxation and operand shapes
Assisted-by: GLM 5.3 Flash
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2026-09-20 14:25:47 +02:00 |
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petrbalvin
|
9b238a525a
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feat(arm64): wide immediates, SIMD compare and system operand forms
Assisted-by: GLM 5.3 Flash
|
2026-09-20 14:25:47 +02:00 |
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petrbalvin
|
6c672567f3
|
feat(amd64): assemble the double-shift and static-SB operand shapes
Assisted-by: GLM 5.3 Flash
|
2026-09-20 11:40:39 +02:00 |
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petrbalvin
|
c66a47973a
|
fix(format): preserve square brackets in SIMD operands
Test / test (push) Successful in 2m15s
Assisted-by: GLM 5.3 Flash
|
2026-09-20 09:58:25 +02:00 |
|
petrbalvin
|
de5d9f358e
|
feat(riscv64,loong64): encode AMO atomics, vector slices and bit ops
Assisted-by: GLM 5.3 Flash
|
2026-09-20 06:44:51 +02:00 |
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petrbalvin
|
ca3fdce0e0
|
feat(arm64): encode pairs, atomics, crypto, system and NEON slices
Assisted-by: GLM 5.3 Flash
|
2026-09-20 06:44:51 +02:00 |
|
petrbalvin
|
fc2d92eabd
|
feat(amd64): encode the GOROOT instruction families
Assisted-by: GLM 5.3 Flash
|
2026-09-20 06:44:51 +02:00 |
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petrbalvin
|
8a51b060da
|
feat(cmd): enable loong64 JIT execution, all trampolines qemu-validated
Assisted-by: GLM 5.3
|
2026-09-20 00:57:02 +02:00 |
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petrbalvin
|
f15ff66fb1
|
fix(riscv64): accept the g spelling of the goroutine register
Assisted-by: GLM 5.3
|
2026-09-20 00:38:24 +02:00 |
|
petrbalvin
|
187e4856d3
|
feat(amd64): encode the mixed-width extend family and PMOVMSKB
Assisted-by: GLM 5.3
|
2026-09-20 00:38:24 +02:00 |
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petrbalvin
|
d315a998ce
|
fix(arm64): store-exclusive operand order and large-frame parity
Assisted-by: GLM 5.3
|
2026-09-20 00:38:24 +02:00 |
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petrbalvin
|
e3b35bb817
|
style(testdata): canonical gasm formatting for the verify kernels
Assisted-by: GLM 5.3
|
2026-09-19 23:49:27 +02:00 |
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petrbalvin
|
ebdf14939f
|
fix(loong64): FP immediates through R30 and unsigned branch forms
Assisted-by: GLM 5.3
|
2026-09-19 23:49:13 +02:00 |
|
petrbalvin
|
79a2c16bac
|
fix(riscv64): compressed store offsets, FENCE and branch range checks
Assisted-by: GLM 5.3
|
2026-09-19 23:49:13 +02:00 |
|
petrbalvin
|
401386956c
|
fix(arm64): encode shifts, divides and multiplies and align sizes with emission
Assisted-by: GLM 5.3
|
2026-09-19 23:49:07 +02:00 |
|
petrbalvin
|
f37f183577
|
feat(riscv64): GOROOT instruction shapes, DATA order and offset expressions
Assisted-by: GLM 5.3 Flash
|
2026-09-19 19:58:43 +02:00 |
|
petrbalvin
|
23c001be51
|
feat(asm): encode indirect JMP and CALL on all four architectures
Assisted-by: GLM 5.3 Flash
|
2026-09-19 19:17:07 +02:00 |
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petrbalvin
|
03d6d4da54
|
style: put the repository assembly in gasm fmt canonical form
Assisted-by: GLM 5.3 Flash
|
2026-09-17 20:33:18 +02:00 |
|
petrbalvin
|
0078f7be5c
|
style: purge em dashes from the produced text
Assisted-by: GLM 5.3 Flash
|
2026-09-16 23:12:31 +02:00 |
|
petrbalvin
|
40476546df
|
fix(asm): close the oracle parity gaps in frame addressing and calls
|
2026-09-14 23:25:14 +02:00 |
|
petrbalvin
|
8f84dac10b
|
feat(verify): ABI checks on arm64, riscv64 and loong64
Assisted-by: GLM 5.3 Flash
|
2026-08-30 11:27:54 +02:00 |
|
petrbalvin
|
97951cbeb6
|
feat(asm): extend arm64 encoder with atomics, bitfield, SIMD and more test kernels
Assisted-by: MiMo V2.5 Pro
|
2026-08-20 14:31:15 +02:00 |
|
petrbalvin
|
6e73f59e78
|
feat(asm): extend arm64 encoder with FP, conditional select, CRC32 and tests
Assisted-by: MiMo V2.5 Pro
|
2026-08-20 14:07:12 +02:00 |
|
petrbalvin
|
4221ec5741
|
feat(asm): add AArch64 arm64 encoder with ground-truth verification
Assisted-by: MiMo V2.5 Pro
|
2026-08-20 13:33:39 +02:00 |
|
petrbalvin
|
c05c53452f
|
fix(asm): encode RISC-V CALL sym(SB) as JAL
Test / vet (push) Successful in 47s
Test / test (push) Failing after 2m9s
Test / build (push) Skipped
Assisted-by: DeepSeek V4 Pro
|
2026-08-13 18:12:22 +02:00 |
|
petrbalvin
|
681a449c01
|
fix(asm): match RISC-V branch and jump encodings
|
2026-08-13 17:57:10 +02:00 |
|
petrbalvin
|
31a2cee382
|
fix(asm): materialise RISC-V MOV immediates
Test / vet (push) Successful in 44s
Test / test (push) Failing after 1m56s
Test / build (push) Skipped
|
2026-08-13 17:41:16 +02:00 |
|
petrbalvin
|
3bc7c18bc3
|
fix(asm): materialise large RISC-V immediates
Assisted-by: DeepSeek V4 Pro
|
2026-08-13 16:04:08 +02:00 |
|
petrbalvin
|
f0512a4e1c
|
fix(asm): complete RISC-V compressed loads/stores and word arithmetic
Assisted-by: DeepSeek V4 Pro
|
2026-08-13 15:42:38 +02:00 |
|
petrbalvin
|
373c09f725
|
fix(asm): correct RISC-V operand order and complete RVC compression
Assisted-by: DeepSeek V4 Pro
|
2026-08-13 15:13:31 +02:00 |
|
petrbalvin
|
b78b6c5004
|
fix(asm): correct RISC-V frame layout and RVC encodings
Assisted-by: GLM 5.2
|
2026-08-13 14:41:57 +02:00 |
|
petrbalvin
|
31ee8e7941
|
feat(asm): add LoongArch encoder with ELF and GOOBJ emission
Assisted-by: DeepSeek V4 Pro
|
2026-08-13 11:24:44 +02:00 |
|
petrbalvin
|
f5088c52fc
|
feat(verify): add runtime ABI checks with sentinel registers and red-zone canary
Assisted-by: Qwen 3.8 Max Preview
|
2026-08-02 23:11:30 +02:00 |
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petrbalvin
|
c9775c2b95
|
feat(verify): add the JIT execution substrate and gasm verify subcommand
Assisted-by: Qwen 3.8 Max Preview
|
2026-08-02 23:11:30 +02:00 |
|